Turbo codes are a new class of codes that can achieve exceptional error performance and energy efficiency at low signal-to-noise ratios. Decoding turbo codes is a complicated procedure that often requires custom hardware if it is to be performed at acceptable speeds. Configurable computing machines are able to provide the performance advantages of custom hardware while maintaining the flexibility of general-purpose microprocessors and DSPs. This thesis presents an implementation of a turbo decoder on an FPGA-based configurable computing platform. Portability and flexibility are emphasized in the implementation so that the decoder can be used as part of a configurable software radio. The system presented performs turbo decoding for a variable block size with a variable number of decoding iterations while using only a single FPGA. When six iterations are performed, the decoder operates at an information bit rate greater than 32 kbps. / Master of Science

As technology evolves and new methods for designing radios arise, it becomes necessary to continue the search for fast and flexible development environments. Some of these new technologies include software defined radio (SDR), Field Programmable Gate Arrays (FPGAs), and the open source project GNU Radio. Software defined radio is a concept that GNU Radio has harnessed to allow developers to quickly create flexible radio designs. In terms of hardware, the maturity of FPGAs give radio designers new opportunities to develop high-speed radios having high-throughput and low-latency, yet the conventional build-time for FPGAs is a limiting factor for productivity. Recent research has lead to reductions in build-time by using FPGAs in a non-traditional manner, meaning productivity no longer has to be sacrificed. The AgileHW project demonstrated this concept and will be used as a basis to develop an overlaying architecture that uses a combination of the technologies mentioned to create a flexible, open, and efficient environment for radio development. This thesis discusses the realization of this architecture with the use of Xilinx FPGAs as a hardware accelerator for an enhanced GNU Radio. / Master of Science

This thesis describes the implementation of a system that can generate two types of image pyramids: the Gaussian pyramid and the Laplacian pyramid. These have been developed using the SPLASH II attached processor, which is a reconfigurable platform based on Field Programmable Gate Arrays (FPGA). The design was first modeled in VHDL, and was then simulated and synthesized to a gate list using a SPLASH II simulator and the Synopsys synthesis tool. The gate list was then mapped onto Xilinx XC4010 FPGA architectures. Three complete designs have been developed to generate pyramids on SPLASH II: two for generating the Gaussian pyramid, and one for generating the Laplacian pyramid. One of the designs produces a complete image pyramid within one image frame time of 33 ms. The other two designs produce complete pyramids within two frame times. All three designs can be used as pipeline stages within a larger image processing system. / Master of Science

The Xilinx Partial Reconfiguration tool kits have been instrumental for performing a wide variety of research on Xilinx FPGAs. These tool kits provide a methodology for creating rectangular partial reconfiguration modules that can be swapped in and out of a static baseline design with one or more PR slots. This thesis presents a new PR toolkit called OpenPR that, for starters, provides similar functionality to the Xilinx PR tool kits. The distinguishing feature of this toolkit is that it is being released as open source, and is intended to be customizable to the needs of researchers. OpenPR has been designed to be easy to use, extensible, portable, and compatible with a wide range of Xilinx software and devices. Aside from supporting the slot-based PR paradigm, OpenPR also provides a solid base for further research into partial reconfiguration and FPGA productivity oriented design tools. / Master of Science

This research consists of the design of a low-power, low-cost, nanosatellite computer system solution. The proposed system solution, and design and implementation of a multiple-bus master FPGA and health monitoring space computer subsystem are described. In the fall of 1998, the US Air Force (USAF) funded Virginia Polytechnic Institute & State University (Virginia Tech), The University of Washington (UW), and Utah State University (USU) with $100,000 each to pursue a formation-flying satellite cluster. The program specified that a cluster of three satellites would maintain radio contact through UHF cross-link communication to report relative positions, obtained through GPS, and coordinate scientific measurement mission activities. This satellite cluster, named Ionospheric Observation Nanosatellite Formation (ION-F) is presently scheduled for launch in June of 2003. Maintaining some degree of system reliability in the error-prone space environment was desired for this low-cost space program. By utilizing high-reliability components in key system locations, and monitoring less reliable portions of the computer system for faults, an improvement in overall system reliability was achieved. The development of a one-wire health monitoring bus master was performed. A Synchronous Serial Peripheral Interface (SPI) bus master was utilized to extend the communication capabilities of the CPU. In addition, discrete I/O functions and A/D converter interfaces were developed for system health monitoring and the spacecraft Attitude Determination and Control System (ADCS). / Master of Science

Two research projects are proposed that rely on Tools for open Reconfigurable Computing (TORC) and the openness of the Xilinx tool chain. The first project, the Embedded FPGA Transmitter, relies on the ability to add arbitrary routes to a physical FPGA which serve no obvious purpose. These routes can then mimic an antenna and transmit directly from the FPGA. This mechanism is not supported utilizing standard hardware description languages; however, the Embedded FPGA Transmitter requires measurements on a real FPGA to determine success. The second project is a back-end tools accelerator designed to reduce the compilation time for FPGA times. As the complexity of FPGAs have exceeded over a million logic cells, the compilation problem size has greatly expanded. The open-source project, TORC, provides an excellent framework for new FPGA research that provides physical, real-world results to ensure the applicability of the research. / Master of Science

A modular reuse-based design methodology has been one of the most important factors in improving hardware design productivity. Traditionally, reuse involves manually searching through repositories for existing components. This search can be tedious and often unfruitful. In order to enhance design reuse, an automated discovery technique is proposed: a reference circuit is compared with an archive of existing designs such that similar circuits are suggested throughout the design phase. To achieve this goal, methods for assessing the similarity of two designs are necessary. Different techniques for comparing the similarity of circuits are explored utilizing concepts from different domains. A new similarity measure was developed using birthmarks that allows for fast and efficient comparison of large and complex designs. Applications where circuit similarity matching can be utilized are examined such as IP theft detection and reverse engineering. Productivity experiments show that automatically suggesting reusable designs to the user could potentially increase productivity by more than 34% on average. / Ph. D.

Bitstream generation has traditionally been the single part of the FPGA design flow that has not been openly reproduced. This work enables bitstream generation for "limited" resources without reverse-engineering or violating End-User License Agreement terms. Two use cases in particular have motivated this work--embedded bitstream generation and fast bitstream generation for small changes in design--both of which are not feasible with the Xilinx's bitstream generation tool. The approach is to first define a set of primitives which can implement an arbitrary digital design and create a library of micro-bitstreams of the primitives. An input design is then mapped to the set of primitives and a bitstream for the design is generated by merging the corresponding micro-bitstreams. This work uses architectural primitives. Initial support is limited to the Virtex-5 and Virtex-7 family of FPGAs from Xilinx, but it can be extended to other Xilinx architectures. Nearly all routing resources in the device, as well as the most common logic resources are supported by this work. / Master of Science

FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors that arise from electromigration effects. Several Built-In Self-Test (BIST) techniques have been proposed in the past to detect and isolate such faults. These techniques suffer from routing congestion problems in modern FPGAs that have a large number of logic blocks. This thesis presents an improved BIST architecture for all Xilinx 7-Series FPGAs that is scalable to large arrays. The two primary sources of overhead associated with FPGA BIST, the test time and the memory required for storing the BIST configurations, are also reduced when compared to previous FPGA-BIST approaches. The BIST techniques presented here also eliminate the need for using any of the user I/O pins, such as a clock, a reset, and test observation pins; therefore, it is suitable for immediate deployment on any system with Xilinx 7-Series FPGAs. With faults detected, isolated, and corrected, the effective MTBF of a system can be extended. / Master of Science

The quick growth of embedded systems and their increasing computing power has made them suitable for a wider range of applications. Despite the increasing performance of modern embedded processors, they are outpaced by computational demands of the growing number of modern applications. This trend has led to emergence of hardware accelerators in embedded systems. While the processing power of dedicated hardware modules seems appealing, they require significant effort of development and integration to gain performance benefit. Thus, it is prudent to investigate and estimate the integration overhead and consequently the hardware acceleration benefit before committing to implementation. In this work, we present FPGA-Roofline, a visual model that offers insights to designers and developers to have realistic expectations of their system and that enables them to do their design and analysis in a faster and more efficient fashion. FPGA-Roofline allows simultaneous analysis of communication and computation resources in FPGA-based hardware accelerators. To demonstrate the effectiveness of our model, we have implemented hardware accelerators in FPGA and used our model to analyze and optimize the overall system performance. We show how the same methodology can be applied to the design process of any FPGA-based hardware accelerator to increase productivity and give insights to improve performance and resource utilization by finding the optimal operating point of the system. / Master of Science