This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second signaling rates. These interfaces are becoming more prevalent in emerging designs and are difficult to test using traditional automated test equipment (ATE) and test instrumentation which were designed for testing designs utilizing synchronous and deterministic signaling. The main motivation of this research was to develop solutions that address these challenges. The methods shown in this thesis are used to design a test architecture consisting of custom hardware components, reprogrammable digital logic for hardware integration, and a software interface for external data transport and configuration. The hardware components consist of a multi-GHz field programmable gate array (FPGA) based interface board providing processing, control, and data capabilities to the system and enhanced by one or more application modules which can be tailored for specific test functionality compatible with source-synchronous and protocol interfaces. Software controls from a host computer provide high and low level access to the internal tester data and configuration memory space. The architecture described in this thesis is demonstrated through a specific test solution for a high-speed optical packet switched network called the Data Vortex. Reprogrammable firmware and software controls allow for a high degree of adaptability and application options. The modularized implementation of the hardware elements introduces additional adaptability and future upgradability, capable of incorporating new materials and design techniques for the test platform and application modules.

This dissertation exammes two of the rlsing technologies in the world of wireless, cellular communications - CDMA and the software radio. This thesis covers many of the issues related to these two emerging field s of wireless communications, establish ing a theoretical framework for the broader issues of implementation. To this end, the thesis covers many of the basic issues of spread spectrum communications, in addition to establishing the need for, and defining the role of, the software radio. Amalgamation of these two key areas of interest is embellished in a presentation of many of the concerns of implementing a specific CDMA system on a particular type of software radio - the Alcatel Altech Telecomms Flexible Radio Platform. Of primary concern in the research methodology embraced in this thesis is the mastering of a variety of analysis and implementation tools. Once the theoretical background has been substantiated by current expositions, the thesis launches along a highly deterministic route. First, the research issues are tested in a mathematical environment for suitability to the given task. Second, an analysis of the appropriateness of the technique for the software radio environment is undertaken, culminating in the attempted deployment within the hardware environmenl. Rigorous testing of the input/output mapping characteristics of the hardware instantiations created in this manner complements the research methodology with a viability study. This procedure is repeated with many elements of the CDMA system design as they are examined, simu lated, deployed and tested. / Thesis (M.Sc.Eng.)-University of Natal, Durban, 2000.

Recent advances in power electronics have lead to the wide spread adoption of advanced power supplies and energy efficient devices. This has lead to increased levels of harmonic currents in power systems, degrading the performance of electrical machinery and interfering with telecommunication services. Active filters provide a solution to these problems by compensating for the distorted currents drawn by non-linear loads. Optimal methods for controlling these active filters have been determined by computer simulation and experimental implementation. Methods used for isolating the harmonic content of an unbalanced three phase load current were compared by computer simulations. A technique based on the Fast Fourier Transform (FFT) was developed as part of this work and shown to perform favourably. Notch Filtering, Sinusoidal Subtraction, Instantaneous Reactive Power Theory, Synchronous Reference Frame and Fast Fourier Transform methods were simulated. The methods shown to be suitable for compensation of three phase unbalanced loads were implemented in a Digital Signal Processor to evaluate true performance. These methods were Notch Filtering, Sinusoidal Subtraction, Fast Fourier Transform, and a High Pass Filter based method. A completely digital hysteresis current controller for a three phase active filter inverter has been developed and implemented with a Field Programmable Gate Array. This controller interfaces directly to a digital signal processor and is resistant to electromagnetic interference. Results from the experimental hardware verified that the active filter model used for simulation is accurate, and may be used for further development of harmonic isolation methods. A technique using notch filtering gives the best performance for steady loads, with the FFT based technique giving the most flexible operation for a range of load current characteristics. Novel use of the FFT based harmonic isolation technique allows selective cancellation of individual harmonics, with particular application to multiple shunt filters connected in parallel.

While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. Two FPAAs, built using Multiple Input Translinear Elements (MITEs), have been designed, fabricated, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, current splitters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. Supporting circuitry for interfacing with current-mode, translinear FPAAs has also been developed. This circuitry included a voltage-to-current converter, a current-to-voltage converter, and a pipelined analog-to-digital converter. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.

Thesis (M.S.)--University of Alabama at Birmingham, 2008. / Description based on contents viewed Oct. 7, 2008; title from PDF t.p. Includes bibliographical references (p. 80-81).

Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographic resources (p.88-89).

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. / Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.

Thesis (M.Eng.)--Memorial University of Newfoundland, 1999. / Bibliography: leaves 100-102.

Submitted by Marcio Filho (marcio.kleber@ufba.br) on 2017-06-02T13:48:59Z No. of bitstreams: 1 Dissertação - Eder Santana Freire - Revisão Final.pdf: 2884218 bytes, checksum: 8fe133e4eb9b646336edaa01f6baba6a (MD5) / Approved for entry into archive by Vanessa Reis (vanessa.jamile@ufba.br) on 2017-06-08T11:16:24Z (GMT) No. of bitstreams: 1 Dissertação - Eder Santana Freire - Revisão Final.pdf: 2884218 bytes, checksum: 8fe133e4eb9b646336edaa01f6baba6a (MD5) / Made available in DSpace on 2017-06-08T11:16:24Z (GMT). No. of bitstreams: 1 Dissertação - Eder Santana Freire - Revisão Final.pdf: 2884218 bytes, checksum: 8fe133e4eb9b646336edaa01f6baba6a (MD5) / O projeto de hardware especializado para detecção de intrusão em redes de computadores tem sido objeto de intensa pesquisa ao longo da última década, devido ao seu desempenho consideravelmente maior, comparado às implementações em software. Nesse contexto, um dos fatores limitantes é a quantidade finita de recursos de memória embarcada, em contraste com o crescente número de padrões de ameaças a serem analisados. Este trabalho propõe uma arquitetura baseada no algoritmo de Huffman para codificação, armazenamento e decodificação paralela de tais padrões, a fim de reduzir o consumo de memória embarcada em projetos de hardware destinado à detecção de intrusão em redes. Experimentos foram realizados através de simulação e síntese em FPGA de conjuntos de regras atuais do sistema de detecção de intrusão Snort, e os resultados indicaram uma economia de até 73% dos recursos de memória embarcada do chip. Adicionalmente, a utilização de uma estrutura paralelizada apresentou ganhos de desempenho significantes durante o processo de decodificação das regras.

Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2014. / The application of digital control techniques has become dominant in power electronics owing to several advantages they present, when compared to analogue solutions. Their development is based on the use of microprocessors and microcontrollers, such as Application Specific Integrated Circuit (ASIC), Digital signal processors (DSP), Field Programmable Gate Arrays (FPGA), or a combination of these devices. This thesis presents an investigation of a soft-core based FPGA control system as a solution for power electronic applications. The aim was the development and implementation of a conversion controller, which purpose is to supply control inputs in the form of digital Pulse Width Modulation (PWM) signals, to a number of power electronic applications, such as single half and full bridge DC-DC converters, three phase and multicell inverters. The PWM control technique is achieved via their power semiconductor switching devices. These PWM control signals are necessary for the high frequency conversion of an analog input voltage (AC, DC or unregulated) to an analog output voltage of another level (AC or DC). This was intended to be achieved by exploiting and combining the advantages that FPGA and embedded processors provide such as high reconfigurability and multipurpose ability. This controller’s digital outputs, namely PWM switching signals, can be directly delivered to an analog signal amplification circuit to create an adequate voltage level before being processed by the converters’ switches.