The increasing demand for energy efficient computing has endorsed the usage of Field-Programmable Gate Arrays to create hardware accelerators for large and complex codes. However, implementing such accelerators involve two complex decisions. The first one lies in deciding which code snippet is the best to create an accelerator, and the second one lies in how to implement the accelerator. When considering both decisions concomitantly, the problem becomes more complicated since the code snippet implementation affects the code snippet choice, creating a combined design space to be explored. As such, a fast design space exploration for the accelerators implementation is crucial to allow the exploration of different code snippets. However, such design space exploration suffers from several time-consuming tasks during the compilation and evaluation steps, making it not a viable option to the snippets exploration. In this work, we focus on the efficient implementation of pipelined hardware accelerators and present our contributions on speeding up the pipelines creation and their design space exploration. Towards loop pipelining, the proposed approaches achieve up to 100× speed-up when compared to the state-uf-the-art methods, leading to 164 hours saving in a full design space exploration with less than 1% impact in the final results quality. Towards design space exploration, the proposed methods achieve up to 9:5× speed-up, keeping less than 1% impact in the results quality. / A demanda crescente por computação energeticamente eficiente tem endossado o uso de Field- Programmable Gate Arrays para a criação de aceleradores de hardware para códigos grandes e complexos. Entretanto, a implementação de tais aceleradores envolve duas decisões complexas. O primeiro reside em decidir qual trecho de código é o melhor para se criar o acelerador, e o segundo reside em como implementar tal acelerador. Quando ambas decisões são consideradas concomitantemente, o problema se torna ainda mais complicado dado que a implementação do trecho de código afeta a seleção dos trechos de código, criando um espaço de projeto combinatorial a ser explorado. Dessa forma, uma exploração do espaço de projeto rápida para a implementação de aceleradores é crucial para habilitar a exploração de diferentes trechos de código. Contudo, tal exploração do espaço de projeto é impedida por várias tarefas que consumem tempo durante os passos de compilação a análise, o que faz da exploração de trechos de códigos inviável. Neste trabalho, focamos na implementação eficiente de aceleradores pipeline em hardware e apresentamos nossas contribuições para o aceleramento da criações de pipelines e de sua exploração do espaço de projeto. Referente à criação de pipelines, as abordagens propostas alcançam uma aceleração de até 100× quando comparadas às abordagens do estado-da-arte, levando à economia de 164 horas em uma exploração de espaço de projeto completa com menos de 1% de impacto na qualidade dos resultados. Referente à exploração do espaço de projeto, as abordagens propostas alcançam uma aceleração de até 9:5×, mantendo menos de 1% de impacto na qualidade dos resultados.

Este trabalho aborda diversas técnicas de controle, com o intuito de comparação do desempenho e robustez ao aplicá-los a um conversor Buck. Iniciando pelo controlador PID (Proporcional, Integral e Derivativo), amplamente explorado e dominado no meio industrial, ele é adotado neste trabalho como referência de comparação para as demais técnicas desenvolvidas. Outra estratégia aqui apresentada é o GANLPID (Gaussian Adaptative Non Linear PID ou PID Adaptativo Não Linear Gaussiano), trata-se de uma técnica não linear, possui ganhos variantes em função do erro baseados em uma função gaussiana. O controle por alocação de polos é uma técnica de controle que em sua forma básica não possui parcela integral, sendo necessária a inclusão deste termo para minimizar o erro em regime permanente. As principais características de análise de desempenho são o tempo de acomodação e overshoot. Todas as técnicas são exploradas a fim de serem implementadas em dispositivos FPGA (Field Programmable Gate Array), possuindo algumas vantagens sobre microcontroladores e DSP’s (Digital Signal Processor), pois conseguem executar tarefas em paralelo deixando a execução do algoritmo mais rápida. As técnicas de controle escolhidas foram simuladas utilizando a ferramenta DSP Builder e compiladas diretamente em código HDL (linguagem de descrição de hardware). Os resultados de simulação e experimentais são apresentados e comentados para validar os projetos propostos. / This work discuss several techniques of control, with an intention of comparison of performance and robustness to apply them to Buck coverter. Starting with PID (Proportional, Integral, Derivative) controller, widely explored and dominated in an industrial environment, it’s used in this work as comparison reference for the others techniques developed. Another strategy presented here is the GANLPID (Gaussian Adaptative Non LinearPID), it’s a case of non linear technique, has won variants in function of the based on a Gaussian error function. variants have gains on function of error based on a Gaussian function. The pole placement control technique not having full part in their basic forms, being necessary to include this term to eliminate the steady-state error. The main performance analysis features are the settling time and overshoot. All the techniques are explored in order to be implemented in FPGA (Field Programmable Gate Array) devices, having some advantages over microcontrollers and DSP’s (Digital Signal Processor), because can execute tasks in parallel allowing the implementation of the algorithm more faster. The chosen control techniques were simulated using the DSP Builder tool and and compiled directly in HDL (hardware description language) code. The results of simulation and experimental are presented and discussed in order to validate the proposed projects.

The new Field Programmable Gate Array (FPGA) technologies and their structures have opened up new approaches to logic design and synthesis. The main feature of an FPGA is an array of logic blocks surrounded by a programmable interconnection structure. Cellular FPGAs are a special class of FPGAs which are distinguished by their fine granularity and their emphasis on local cell interconnects. While these characteristics call for specialized synthesis tools, the availability of logic gates other than Boolean AND, OR and NOT in these architectures opens up new possibilities for synthesis. Among the possible realizations of Boolean functions, XOR logic is shown to be more compact than AND/OR and also highly testable. In this dissertation, the concept of structural regularity and the advantages of XOR logic are used to investigate various synthesis approaches to cellular FPGAs, which up to now have been mostly nonexistent. Universal XOR Canonical Forms, Two-level AND/XOR, restricted factorization, as well as various Directed Acyclic Graph structures are among the proposed approaches. In addition, a new comprehensive methodology for the investigation of all possible XOR canonical forms is introduced. Additionally, a new compact class of XOR-based Decision Diagrams for the representation of Boolean functions, called Kronecker Functional Decision Diagrams (KFDD), is presented. It is shown that for the standard, hard, benchmark examples, KFDDs are on average 35% more compact than Binary Decision Diagrams, with some reductions of up to 75% being observed.

<p>The most important aspects of nuclear medicine imaging systems such as Positron Emission Tomography (PET) or Single Photon Emission Computed Tomography (SPECT) are the spatial resolution and the sensitivity (detector efficiency in combination with the geometric efficiency). Considerable efforts have been spent during the last two decades in improving the resolution and the efficiency by developing new detectors. Our proposed improvement technique is focused on the readout and electronics. Instead of using traditional pulse height analysis techniques we propose using free running digital sampling by replacing the analog readout and acquisition electronics with fully digital programmable systems.</p><p>This thesis describes a fully digital data acquisition system for KS/SU SPECT, new algorithms for high resolution timing for PET, and modular FPGA based decentralized data acquisition system with optimal timing and energy. The necessary signal processing algorithms for energy assessment and high resolution timing are developed and evaluated. The implementation of the algorithms in field programmable gate arrays (FPGAs) and digital signal processors (DSP) is also covered. Finally, modular decentralized digital data acquisition systems based on FPGAs and Ethernet are described.</p>

<p>The Stressometer system is a measurement and control system used in cold rolling to improve the flatness of a metal strip. In order to achieve this goal the system employs a multiple input multiple output (MIMO) control system that has a considerable number of sensors and actuators. As a consequence the computational load on the Stressometer control system becomes very high if too advance functions are used. Simultaneously advances in rolling mill mechanical design makes it necessary to implement more complex functions in order for the Stressometer system to stay competitive. Most industrial players in this market considers improved computational power, for measurement, control and modeling applications, to be a key competitive factor. Accordingly there is a need to improve the computational power of the Stressometer system. Several different approaches towards this objective have been identified, e.g. exploiting hardware parallelism in modern general purpose and graphics processors.</p><p>Another approach is to implement different applications in FPGA-based hardware, either tailored to a specific problem or as a part of hardware/software co-design. Through the use of a hardware/software co-design approach the efficiency of the Stressometer system can be increased, lowering overall demand for processing power since the available resources can be exploited more fully. Hardware accelerated platforms can be used to increase the computational power of the Stressometer control system without the need for major changes in the existing hardware. Thus hardware upgrades can be as simple as connecting a cable to an accelerator platform while hardware/software co-design is used to find a suitable hardware/software partition, moving applications between software and hardware.</p><p>In order to determine whether this hardware/software co-design approach is realistic or not, the feasibility of implementing simulator, computational and control applications in FPGAbased hardware needs to be determined. This is accomplished by selecting two specific applications for a closer study, determining the feasibility of implementing a Stressometer measuring roll simulator and a parallel Cholesky algorithm in FPGA-based hardware.</p><p>Based on these studies this work has determined that the FPGA device technology is perfectly suitable for implementing both simulator and computational applications. The Stressometer measuring roll simulator was able to approximate the force and pulse signals of the Stressometer measuring roll at a relative modest resource consumption, only consuming 1747 slices and eight DSP slices. This while the parallel FPGA-based Cholesky component is able to provide performance in the range of GFLOP/s, exceeding the performance of the personal computer used for comparison in several simulations, although at a very high resource consumption. The result of this thesis, based on the two feasibility studies, indicates that it is possible to increase the processing power of the Stressometer control system using the FPGA device technology.</p>

The most important aspects of nuclear medicine imaging systems such as Positron Emission Tomography (PET) or Single Photon Emission Computed Tomography (SPECT) are the spatial resolution and the sensitivity (detector efficiency in combination with the geometric efficiency). Considerable efforts have been spent during the last two decades in improving the resolution and the efficiency by developing new detectors. Our proposed improvement technique is focused on the readout and electronics. Instead of using traditional pulse height analysis techniques we propose using free running digital sampling by replacing the analog readout and acquisition electronics with fully digital programmable systems. This thesis describes a fully digital data acquisition system for KS/SU SPECT, new algorithms for high resolution timing for PET, and modular FPGA based decentralized data acquisition system with optimal timing and energy. The necessary signal processing algorithms for energy assessment and high resolution timing are developed and evaluated. The implementation of the algorithms in field programmable gate arrays (FPGAs) and digital signal processors (DSP) is also covered. Finally, modular decentralized digital data acquisition systems based on FPGAs and Ethernet are described.

The Stressometer system is a measurement and control system used in cold rolling to improve the flatness of a metal strip. In order to achieve this goal the system employs a multiple input multiple output (MIMO) control system that has a considerable number of sensors and actuators. As a consequence the computational load on the Stressometer control system becomes very high if too advance functions are used. Simultaneously advances in rolling mill mechanical design makes it necessary to implement more complex functions in order for the Stressometer system to stay competitive. Most industrial players in this market considers improved computational power, for measurement, control and modeling applications, to be a key competitive factor. Accordingly there is a need to improve the computational power of the Stressometer system. Several different approaches towards this objective have been identified, e.g. exploiting hardware parallelism in modern general purpose and graphics processors. Another approach is to implement different applications in FPGA-based hardware, either tailored to a specific problem or as a part of hardware/software co-design. Through the use of a hardware/software co-design approach the efficiency of the Stressometer system can be increased, lowering overall demand for processing power since the available resources can be exploited more fully. Hardware accelerated platforms can be used to increase the computational power of the Stressometer control system without the need for major changes in the existing hardware. Thus hardware upgrades can be as simple as connecting a cable to an accelerator platform while hardware/software co-design is used to find a suitable hardware/software partition, moving applications between software and hardware. In order to determine whether this hardware/software co-design approach is realistic or not, the feasibility of implementing simulator, computational and control applications in FPGAbased hardware needs to be determined. This is accomplished by selecting two specific applications for a closer study, determining the feasibility of implementing a Stressometer measuring roll simulator and a parallel Cholesky algorithm in FPGA-based hardware. Based on these studies this work has determined that the FPGA device technology is perfectly suitable for implementing both simulator and computational applications. The Stressometer measuring roll simulator was able to approximate the force and pulse signals of the Stressometer measuring roll at a relative modest resource consumption, only consuming 1747 slices and eight DSP slices. This while the parallel FPGA-based Cholesky component is able to provide performance in the range of GFLOP/s, exceeding the performance of the personal computer used for comparison in several simulations, although at a very high resource consumption. The result of this thesis, based on the two feasibility studies, indicates that it is possible to increase the processing power of the Stressometer control system using the FPGA device technology.

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. Recent advances in the area of floating-gate transistors have led to an analog technology that is very small, accurately programmable, and extremely low in power consumption. By leveraging the advantages of floating-gate devices, a large-scale FPAA is designed that dramatically advances the current state of the art in terms of size, functionality, and flexibility. A large-scale FPAA is used as part of a mixed-signal prototyping platform to demonstrate the viability and benefits of cooperative analog/digital signal processing. This work serves as a roadmap for future FPAA research. While current FPAAs can be compared with the small, relatively limited, digital, programmable logic devices (PLDs) of the 1970s and 1980s, the floating-gate FPAAs introduced here are the first step in enabling FPAAs to support large-scale, full-system prototyping of analog designs similar to modern FPGAs.

With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment. Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques. These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic architecture.

The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.