Le chiffrement homomorphe est une branche de la cryptologie, dans laquelle les schémas de chiffrement offrent la possibilité de faire des calculs sur les messages chiffrés, sans besoin de les déchiffrer. L’intérêt pratique de ces schémas est dû à l’énorme quantité d'applications pour lesquels ils peuvent être utilisés. En sont un exemple le vote électronique, les calculs sur des données sensibles, comme des données médicales ou financières, le cloud computing, etc..Le premier schéma de chiffrement (complètement) homomorphe n'a été proposé qu'en 2009 par Gentry. Il a introduit une technique appelée bootstrapping, utilisée pour réduire le bruit des chiffrés : en effet, dans tous les schémas de chiffrement homomorphe proposés, les chiffrés contiennent une petite quantité de bruit, nécessaire pour des raisons de sécurité. Quand on fait des calculs sur les chiffrés bruités, le bruit augmente et, après avoir évalué un certain nombre d’opérations, ce bruit devient trop grand et, s'il n'est pas contrôlé, risque de compromettre le résultat des calculs.Le bootstrapping est du coup fondamental pour la construction des schémas de chiffrement homomorphes, mais est une technique très coûteuse, qu'il s'agisse de la mémoire nécessaire ou du temps de calcul. Les travaux qui on suivi la publication de Gentry ont eu comme objectif celui de proposer de nouveaux schémas et d’améliorer le bootstrapping pour rendre le chiffrement homomorphe faisable en pratique. L’une des constructions les plus célèbres est GSW, proposé par Gentry, Sahai et Waters en 2013. La sécurité du schéma GSW se fonde sur le problème LWE (learning with errors), considéré comme difficile en pratique. Le bootstrapping le plus rapide, exécuté sur un schéma de type GSW, a été proposé en 2015 par Ducas et Micciancio. Dans cette thèse on propose une nouvelle variante du schéma de chiffrement homomorphe de Ducas et Micciancio, appelée TFHE.Le schéma TFHE améliore les résultats précédents, en proposant un bootstrapping plus rapide (de l'ordre de quelques millisecondes) et des clés de bootstrapping plus petites, pour un même niveau de sécurité. TFHE utilise des chiffrés de type TLWE et TGSW (scalaire et ring) : l’accélération du bootstrapping est principalement due à l’utilisation d’un produit externe entre TLWE et TGSW, contrairement au produit externe GSW utilisé dans la majorité des constructions précédentes.Deux types de bootstrapping sont présentés. Le premier, appelé gate bootstrapping, est exécuté après l’évaluation homomorphique d’une porte logique (binaire ou Mux) ; le deuxième, appelé circuit bootstrapping, peut être exécuté après l’évaluation d’un nombre d'opérations homomorphiques plus grand, pour rafraîchir le résultat ou pour le rendre compatible avec la suite des calculs.Dans cette thèse on propose aussi de nouvelles techniques pour accélérer l’évaluation des calculs homomorphiques, sans bootstrapping, et des techniques de packing des données. En particulier, on présente un packing, appelé vertical packing, qui peut être utilisé pour évaluer efficacement des look-up table, on propose une évaluation via automates déterministes pondérés, et on présente un compteur homomorphe appelé TBSR qui peut être utilisé pour évaluer des fonctions arithmétiques.Pendant les travaux de thèse, le schéma TFHE a été implémenté et il est disponible en open source.La thèse contient aussi des travaux annexes. Le premier travail concerne l’étude d’un premier modèle théorique de vote électronique post-quantique basé sur le chiffrement homomorphe, le deuxième analyse la sécurité des familles de chiffrement homomorphe dans le cas d'une utilisation pratique sur le cloud, et le troisième ouvre sur une solution différente pour le calcul sécurisé, le calcul multi-partite. / Fully homomorphic encryption is a new branch of cryptology, allowing to perform computations on encrypted data, without having to decrypt them. The main interest of homomorphic encryption schemes is the large number of practical applications for which they can be used. Examples are given by electronic voting, computations on sensitive data, such as medical or financial data, cloud computing, etc..The first fully homomorphic encryption scheme has been proposed in 2009 by Gentry. He introduced a new technique, called bootstrapping, used to reduce the noise in ciphertexts: in fact, in all the proposed homomorphic encryption schemes, the ciphertexts contain a small amount of noise, which is necessary for security reasons. If we perform computations on noisy ciphertexts, the noise increases and, after a certain number of operations, the noise becomes to large and it could compromise the correctness of the final result, if not controlled.Bootstrapping is then fundamental to construct fully homomorphic encryption schemes, but it is very costly in terms of both memory and time consuming.After Gentry’s breakthrough, the presented schemes had the goal to propose new constructions and to improve bootstrapping, in order to make homomorphic encryption practical. One of the most known schemes is GSW, proposed by Gentry, Sahai et Waters in 2013. The security of GSW is based on the LWE (learning with errors) problem, which is considered hard in practice. The most rapid bootstrapping on a GSW-based scheme has been presented by Ducas and Micciancio in 2015. In this thesis, we propose a new variant of the scheme proposed by Ducas and Micciancio, that we call TFHE.The TFHE scheme improves previous results, by performing a faster bootstrapping (in the range of a few milliseconds) and by using smaller bootstrapping keys, for the same security level. TFHE uses TLWE and TGSW ciphertexts (both scalar and ring): the acceleration of bootstrapping is mainly due to the replacement of the internal GSW product, used in the majority of previous constructions, with an external product between TLWE and TGSW.Two kinds of bootstrapping are presented. The first one, called gate bootstrapping, is performed after the evaluation of a homomorphic gate (binary or Mux); the second one, called circuit bootstrapping, can be executed after the evaluation of a larger number of homomorphic operations, in order to refresh the result or to make it compatible with the following computations.In this thesis, we also propose new techniques to improve homomorphic computations without bootstrapping and new packing techniques. In particular, we present a vertical packing, that can be used to efficiently evaluate look-up tables, we propose an evaluation via weighted deterministic automata, and we present a homomorphic counter, called TBSR, that can be used to evaluate arithmetic functions.During the thesis, the TFHE scheme has been implemented and it is available in open source.The thesis contains also ancillary works. The first one concerns the study of the first model of post-quantum electronic voting based on fully homomorphic encryption, the second one analyzes the security of homomorphic encryption in a practical cloud implementation scenario, and the third one opens up about a different solution for secure computing, multi-party computation.

京都大学 / 0048 / 新制・課程博士 / 博士(理学) / 甲第18801号 / 理博第4059号 / 新制||理||1584(附属図書館) / 31752 / 京都大学大学院理学研究科地球惑星科学専攻 / (主査)教授 岩田 知孝, 教授 平原 和朗, 准教授 久家 慶子 / 学位規則第4条第1項該当 / Doctor of Science / Kyoto University / DGAM

No

Modern communication systems face new technological challenges, such as the narrowness and overload of the conventional frequency bands employed for these applications. Nowadays, communication systems are expected to operate at higher frequencies, such as the mm-wave band. In particular, for space applications, specific environmental conditions make it necessary to design low-profile, lightweight and high gain systems with wide-angle scanning capabilities. Traditional solutions are reflectors antennas or planar arrays. Reflectors often end up being bulky, whereas array antennas are lossy and costly. Lens antennas, unpopular at low frequencies due to their large size, offer a better solution in this context, due to their focusing properties, wide-scanning capability, and broadband behaviour. Among lens antennas, geodesic lens antennas have recently increased interest since they are fullymetallic and easy to manufacture. Previous research aiming at reducing the profile of geodesic lens antennas, while preserving high performances, allowed a total height reduction by a factor 4. In this work, I investigate the possibility of reducing the profile even further by following a different approach. Instead of folding by mirroring the curved profile, the lens antenna is built with circular ridge structures, in an attempt to discretize the original profile. Different approaches have been proposed. First, designs with different numbers of squared ridges were proposed. The reflections are reduced by chamfering the corners of the ridges. Moreover, triangle ridges and alternating the ridges orientation have also been investigated. The final design has four squared ridges with the same orientation. This design was chosen due to its radiation performance. This approach reduces the profile by a factor 18. A prototype has been manufactured working on the frequency band [24,34] GHz. The scanning range is ±62◦ , reflections levels are below -15 dB and at 29 GHz the maximum realized gain is equal to 15.75 dBi. This solution offers attractive properties, mainly due to its compactness. The height of the lens antenna is restricted by the flare, which was set at λ/2. This means that this lens antenna can be stacked in a linear array with grating-lobe-free performance in the elevation plane. / Moderna kommunikationssystem står inför nya tekniska utmaningar, såsom smalheten samt överbelastning inom de konventionella frekvensband som avsatts för tillhörande applikationer. Nutida kommunikationssystem förväntas operera på högre frekvenser, vilket implicerar våglängder på millimeternivå. Särskilt inom rymdapplikationer så finns förutbestämda miljömässiga förhållanden som nödvändiggör användning av lågprofilerade och lättviktiga system med hög antennförstärkning samt möjlighet för vidvinkelskanning. Traditionella lösningar omfattar både reflektorantenner och plana gruppantenner, vilket antingen är otympligt respektive kostsamt. Linsantenner, otympliga och därav opopulära val inom lägre frekvenser, visar sig vara bra lösningar i given kontext. Detta följer av linsernas fokuseringsegenskaper, breda skanningsförmåga samt naturligt stora frekvensband. Inom guppen av linsantenner så har geodetiska linsantenner fått ökat intresse till följd av dess simpla tillverkningsprocess samt fullt metalliska struktur. Tidigare forskning som syftat åt att minska profilen tillsammande med bibehållen prestanda, har lyckats minska höjden men en faktor av fyra. I detta arbete så undersöks möjligheten att krympa profilen ytterligare via användning av ett nytt angreppssätt. I stället för att vika linsen överstämmande med en kurvig profil, så formas linsantennerna med cirkulära ås-strukturer (små böjningar) i strävan efter att diskretisera den ursprunglig profilen. Olika tillvägagångssätt visas i detta arbete. Först visas profiler med ett varierande antal kvadratiska åsar. Reflektioner längs profilen reduceras vid introduktion av fasningar av kvadratens tillhörande hörn. Ytterligare så har triangulära åsar samt riktningen (ås med riktning upp eller riktning ned längs den horisontella profilen) av samtliga typer utvärderats. Den slutliga designen har fyra kvadratiska åsar i samma riktning, ett designval baserat på strålningsprestanda. Arbetet visar att det sistnämnde tillvägagångssättet minskar profilen med en faktor av 18. En fungerande prototyp inom frekvensbandet [24,34] GHz har tillverkats baserat på sistnämnd design, som uppnår ett skanningsområde upp till 62◦ , en reflektionsnivå under -15 dB samt en maximal antennförstärkning på 15.75 dBi vid 29 GHz. Den föreslagna lösningen erhåller attraktiva egenskaper, främst med avseende på dess kompakthet. Höjden på linsantennen begränsas av en matchande flank med en halv våglängd stor öppning, så att flertalet linsantenner kan staplas och forma en linjär gruppantenn vars prestanda utesluter större sidolober längs höjdplanet.

No description available.

<p>Multirotor unmanned aerial vehicles (UAVs) added with the ability to physically interact with the environment has opened endless possibilities for aerial mobile manipulation tasks. With the unlimited reachable workspace and physical interaction capabilities, such robots can enhance human ability to perform dangerous and hard-to-reach tasks. However, realizing aerial mobile manipulation in real-world scenarios is challenging with respect to the diversity in aerial platforms, control fidelity and susceptibility to variations in the environment. Therefore, the first part of the dissertation provides tools to  classify and evaluate different multirotor designs. A measure of responsiveness of a multirotor platform in exerting generalized forces and rejecting disturbances is discussed through the control bandwidth analysis. Superiority in control bandwidth for fully-actuated multirotors is established in a comparison with equivalent under-actuated multirotors. To further classify and distinguish multirotor platforms, a new mobility measure is proposed and compared by surveying all aerial platforms employed for aerial mobile manipulation. In compliance to the control bandwidth analysis, the mobility measure for fully-actuated multirotors is relatively higher making them better suited for manipulation tasks. </p> <p><br></p> <p><br></p> <p>Aerial physical interaction, as a part of aerial mobile manipulation, with partially unknown environments is challenging due to the uncertainties imposed while dexterously exerting force signatures. A hybrid physical interaction (HyPhI) controller is proposed to enable constrained force contact with a steady transition from unconstrained motion, by squelching excess energy during initial impact. However, uncertainties posed by the partially unknown environment requires to understand the surrounding environment and their current physical states, that can enhance interaction performance. The limited resources and flight time of the multirotors requires to simultaneously understand the environment and perform aerial physical interactions. Inspection-on-the-fly is an uncanny ability of humans to intuitively infer states during manipulation while reducing the necessity to conduct inspection and manipulation separately. In this dissertation, the inspection-on-the-fly method based HyPhI controller is proposed to engage in a steady contact with partially unknown environments, while simultaneously estimating the physical states of the surfaces. The proposed method is evaluated in a mockup of real-world facility, to understand the surface properties while engaging in steady interactions. Further, such inspection of surfaces and estimation of various states enables a deeper understanding of the environment while enhancing the ability to physically interact. </p>

[pt] Este trabalho propõe e avalia arquiteturas profundas para o reconhecimento de culturas agrícolas a partir de seqüências de imagens multitemporais de sensoriamento remoto. Essas arquiteturas combinam a capacidade de modelar contexto espacial prórpia de redes totalmente convolucionais com a capacidade de modelr o contexto temporal de redes recorrentes para a previsão prever culturas agrícolas em cada data de uma seqüência de imagens multitemporais. O desempenho destes métodos é avaliado em dois conjuntos de dados públicos. Ambas as áreas apresentam alta dinâmica espaçotemporal devido ao clima tropical/subtropical e a práticas agrícolas locais, como a rotação de culturas. Nos experimentos verificou-se que as arquiteturas propostas superaram os métodos recentes baseados em redes recorrentes em termos de Overall Accuracy (OA) e F1-score médio por classe. / [en] This work proposes and evaluates deep learning architectures for multi-date agricultural crop recognition from remote sensing image sequences. These architectures combine the spatial modelling capabilities of fully convolutional networks and the sequential modelling capabilities of recurrent networks into end-to-end architectures so-called fully convolutional recurrent networks, configured to predict crop type at multiple dates from a multitemporal image sequence. Their performance is assessed over two publicly available datasets. Both datasets present highly spatio-temporal dynamics due to their tropical/sub-tropical climate and local agricultural practices such as crop rotation. The experiments indicated that the proposed architectures outperformed state of the art methods based on recurrent networks in terms of Overall Accuracy (OA) and per-class average F1 score.

Everyone is in need for their own privacy and data protection, since encryption transmission was becoming common. Fully Homomorphic Encryption (FHE) has received increased attention because of its capability to execute calculations over the encoded domain. Through using FHE approach, model training can be properly outsourced. The goal of FHE is to enable computations on encrypted files without decoding aside from the end outcome. The CKKS scheme is used in FHE.Network threats are serious danger to credential information, which enable an unauthorised user to extract important and sensitive data by evaluating the information of computations done on raw data. Thus the study provided an efficient solution to the problem of privacy protection in data-driven applications using Machine Learning. The study used an encrypted NSL KDD dataset. Machine learning-based techniques have emerged as a significant trend for detecting malicious attack. Thus, Random Forest (RF) is proposed for the detection of malicious attacks on Homomorphic encrypted data in the cloud server. Logistic Regression (LR) machine learning model is used to predict encrypted data on cloud server. Regardless of the distributed setting, the technique may retain the accuracy and integrity of the previous methods to obtain the final results.

This work explores the application of various power amplifier design techniques for mobile communications. Several circuit configurations including class A amplifier, Doherty amplifier and power combining amplifier have been developed, which are to improve the performance of power amplifiers in terms of power added efficiency transmission power and bandwidth. In chapter 2, the cascode PA adopting tuning capacitor structure is proposed and implemented to enhance the efficiency. In chapter 3, a novel Doherty amplifier configuration using a 3-stage polyphase filter as power splitter is introduced. Moreover, the second harmonic cancellation function of balun combining PA is analysed and verified with experimental results in chapter 4. The fully integrated cascode class A amplifier adopts RC negative feedback, which is to enhance bandwidth and input/output matching. The integrated choke inductor compensating the parasitic capacitor of transistors has very low quality factor, which decreases the efficiency of the power amplifier. To reduce the inductance value of the choke inductor, a tuning capacitor is connected in parallel with the choke inductor. As a result, the inductor resistance is reduced as well, which diminishes the power consumption induced by the resistance of the choke inductor. This proposed PA configuration is validated by simulation results with the PAE improved by 3 % at the 1 dB compression point compared to the topology without tuning capacitor. The experimental results demonstrate a PA which delivers an output power of 21.3 dBm with PAE of 21 % at the 1 dB compression point. The Doherty amplifier with 2-way Wilkinson power splitter is integrated in a 0.9 mm×1.8 mm chip. The main and peak amplifier adopt cascode configuration to improve the stability of the Doherty amplifier. To minimize the chip size, the quarter wave transmission line in the topology is replaced by π-type lumped element equivalent network. To increase the operating bandwidth, the Doherty amplifier configuration using a 3-stage polyphase filter as power splitter is proposed. The topology consists of 3-stage RC polyphase filter, drive amplifiers, main amplifier, peak amplifier, and impedance inverter. By employing the polyphase filter, the quarter-wave transmission line at the input of the peak amplifier for compensating the phase shift of the impedance inverter is eliminated. According to the analysis of the polyphase filter prototype, the 3-stage polyphase filter is selected, and the component parameters are determined. The main amplifier and peak amplifier are using differential cascode configuration. The drive amplifier is to increase the power gain and provide proper impedance matching for the Doherty amplifier. The results demonstrate an outstanding broadband Doherty amplifier with a bandwidth of 1.8 GHz. The chip temperature rises dramatically due to the high power consumption of power amplifier. Consequently, the collector currents of the SiGe transistors are varying with the changing temperature, which deteriorates the PA performance. In the improved 3-stage PPF Doherty design, the bias voltages of the transistors in the first version 3-stage PPF Doherty amplifier are replaced by reference currents feeding through bias circuits. With current sources providing bias current to the transistors, the performance of the improved Doherty amplifier is enhanced. The power combining PAs are constructed on FR-4 PCB boards using discrete components. The single ended power amplifier in the power combining PA is built with high linearity HEMT transistor. The balun combining PA has an advantage of second harmonic cancellation, which is validated by both analysis and measurements. Moreover, power combining PAs with 2-way transmission line and lumped element Wilkinson power divider are designed. The transmission lines in these designs are analyzed using EM simulation tool and verified with testing structures on PCB boards.

Les circuits intégrés (CI) devenant de plus en plus complexes et vulnérables face aux décharges électrostatiques (ESD pour ElectroStatic Discharge), la capacité à vérifier de manière fiable la présence de défauts de conception ESD sur des puces comptant plusieurs milliards de transistors avant tout envoi en fabrication est devenu un enjeu majeur dans l’industrie des semi-conducteurs. Des outils commerciaux automatisés de dessin électronique (EDA pour Electronic Design Automation) et leur flot de vérification associé permettent d’effectuer différents types de contrôles qui se sont révélés être efficaces pour des circuits avec une architecture classique. Cependant, ils souffrent de limitations lorsqu’ils sont confrontés à des architectures inhabituelles, dites custom. De plus, ces méthodes de vérification sont généralement effectuées tard dans le flot de conception, rendant toute rectification de dessin coûteuse en termes d’efforts correctifs et de temps. Cette thèse de doctorat propose une méthodologie de vérification ESD systématique et multi-échelle introduite dans un outil appelé ESD IP Explorer qui a été spécifiquement implémenté pour couvrir le flot de conception dans sa globalité et pour adresser des circuits dits custom. Il est composé d’un module de reconnaissance et d’un module de vérification. Le module de reconnaissance identifie tout d’abord et de manière automatisée les structures de protection ESD, embarquées sur silicium dans le circuit intégré pour améliorer leur robustesse ESD, selon un mécanisme de reconnaissance topologique. Le module de vérification convertit ensuite le réseau de protection ESD, formé des structures de protection ESD, en un graphe dirigé. Finalement, une analyse ESD quasi-statique reposant sur des algorithmes génériques issus de la théorie des graphes est effectuée sur la globalité du circuit à vérifier. Des algorithmes d’apprentissage automatique ont été employés pour prédire les comportements quasi-statiques des protections ESD à partir des paramètres d’instance de leurs composants élémentaires sous la forme d’une liste d’interconnexions. L’avantage ici est qu’aucune simulation électrique n’est requise pendant toute la durée d’exécution d’ESD IP Explorer, ce qui simplifie l’architecture de l’outil et accélère l’analyse. Les efforts d’implémentation ont été concentrés sur la compatibilité d’ESD IP Explorer avec le nœud technologique 28nm FD-SOI (pour Fully Depleted Silicon On Insulator). L’outil de vérification développé a été utilisé avec succès pour l’analyse d’un circuit incorporant des parties numériques et à signaux mixtes et comprenant plus de 1,5 milliard de transistors en seulement quelques heures. Des circuits custom qui n’ont pas pu être vérifiés au moyen d’outils de vérification traditionnels du fait de problèmes d’incompatibilité ont également pu être soumis à analyse grâce à ESD IP Explorer. / As Integrated Circuits (ICs) become more complex and susceptible to ElectroStatic Discharges (ESD), the ability to reliably verify the presence of ESD design weaknesses over a multi-billion transistor chip prior to the tape-out is a major topic in the semiconductor industry. Commercial tools dedicated to Electronic Design Automation (EDA) and related verification flows are in charge of providing checks that have been proven to be efficient for circuits with a mainstream architecture. However, they suffer limitations when confronted with custom designs. Moreover, these verification methods are often run late in the design flow, making any design re-spin costly in terms of corrective efforts and time. This Ph. D. thesis proposes a systematic and scalable ESD verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. It is composed of a recognition module and a verification module. The recognition module first automatically identifies ESD protection structures, embedded in integrated circuits to enhance their ESD hardness, according to a topology-aware recognition mechanism. The verification module then converts the ESD protection network that is formed by ESD protection structures into a directed graph. There, technology-independent and graph-based verification mechanisms perform a chip-scale quasistatic ESD analysis. Machine learning algorithms have been used in order to infer the quasistatic behavior of ESD IPs from the netlist instance parameters of their primary devices. This approach has the advantage that no simulation is required during the execution of ESD IP Explorer, which makes the tool architecture simpler and improves execution times. Implementation efforts pertained to the compliance of ESD IP Explorer with the 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The developed verification tool has been used to successfully analyze a digital and mixed-signal circuit prototype counting more than 1.5 billion transistors in several hours, as well as custom designs that could not be analyzed by means of traditional verification tools due to incompatibility issues.