Scientific solutions to physical problems are computationally intensive. With the increasing emphasis in the area of Custom Computing Machines, many physical problems are being solved using configurable computers. The Finite Element Method (FEM) is an efficient way of solving physical problems such as heat equations, stress analysis and two- and three-dimensional Poisson's equations. This thesis presents the solution to physical problems using the FEM on a configurable platform. The core computational unit in an iterative solution to the FEM, the matrix-by-vector multiplication, is developed in this thesis along with the framework necessary for implementing the FEM solution. The solutions for 2-D and 3-D Poisson's equations are implemented with the use of an adaptive mesh refinement method. The dominant computation in the method is matrix-by-vector multiplication and is performed on the Wildforce board, a configurable platform. The matrix-by-vector multiplication units developed in this thesis are basic mathematical units implemented on a configurable platform and can be used to accelerate any mathematical solution that involves such an operation. / Master of Science

FPGA implementation tools have not kept pace with growing FPGA density. It is common for non-trivial designs to take multiple hours to go through the entire FPGA toolflow (synthesis, mapping, placement, routing, bitstream generation). FPGA implementation tool runtime is a major hindrance to FPGA Productivity. In modern FPGA designs, designers often change logic and/or connections in an already existing design. If small modifications are made to a particular module in a design, then almost the entire design will go through most of the FPGA toolflow again. This can be time consuming for complex designs and hinder productivity of FPGA designers. The main goal of this thesis is to improve FPGA productivity by reducing FPGA design implementation time for modifications made to an already existing design for rapid system deployment. In this thesis, a toolkit is presented, which is capable of making design modifications at a lower level of abstraction for already existing designs on Xilinx FPGAs. The toolkit is a part of the open-source RapidSmith framework and includes the EDIF parser, mapper, placer, and router. It can be used to change logic and/or modify connections. Modules can be placed, unplaced, relocated, and/or duplicated with ease using this toolkit. Significant time-savings were seen by making use of the toolkit along-with the standard Xilinx FPGA toolflow, for making design modifications to already existing designs. / Master of Science

Data security is becoming ever more important in embedded and portable electronic devices. The sophistication of the analysis techniques used by attackers is amazingly advanced. Digital devices' external interfaces to memory and communications interfaces to other digital devices are vulnerable to malicious probing and examination. A hostile observer might be able to glean important details of a device's design from such an interface analysis. Defensive measures for protecting a device must therefore be even more sophisticated and robust. This thesis presents an architecture that acts as a secure wrapper around an embedded application on a Field Programmable Gate Array (FPGA). The architecture includes functional units that serve to authenticate a user over a secure serial interface, create a key with multiple layers of security, and encrypt an external memory interface using that key. In this way, the wrapper protects all of the digital interfaces of the embedded application from external analysis. Cryptographic methods built into the system include an RSA-related secure key exchange, the Secure Hash Algorithm, a certificate storage system, and the Data Encryption Standard algorithm in counter mode. The principles behind the encrypted external memory interface and the secure authentication interface can be adjusted as needed to form a secure wrapper for a wide variety of embedded FPGA applications. / Master of Science

A very basic engineering tradeoff is performance versus flexibility and this design choice must be made when developing a software radio. Hardware devices such as General Purpose Processors (GPPs), Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) all provide a designer with choices along the performance versus flexibility spectrum. The designer must choose a combination of GPP, DSP, FPGA and ASIC devices to balance the needs of performance versus flexibility. The Software Communications Architecture (SCA) is a specification for a software radio architecture produced by the Joint Program Executive Office (JPEO) Joint Tactical Radio System (JTRS). The 2.2 revision of the SCA only implies support for GPPs, with no specified support for additional devices such as FPGAs. However, FPGA integration within the scope of the SCA is still possible. The integration of an additional processing hardware device other than a GPP requires the ability to logically represent the device within the Core Framework. This representation is implemented within the OSSIE Core Framework, an open source implementation of the SCA. The representation requires the support of multiple implementations of signal processing components within the framework, a simple component deployment model, and the abstraction of the FPGA interactions into a software component. / Master of Science

Turbo codes are a new class of codes that can achieve exceptional error performance and energy efficiency at low signal-to-noise ratios. Decoding turbo codes is a complicated procedure that often requires custom hardware if it is to be performed at acceptable speeds. Configurable computing machines are able to provide the performance advantages of custom hardware while maintaining the flexibility of general-purpose microprocessors and DSPs. This thesis presents an implementation of a turbo decoder on an FPGA-based configurable computing platform. Portability and flexibility are emphasized in the implementation so that the decoder can be used as part of a configurable software radio. The system presented performs turbo decoding for a variable block size with a variable number of decoding iterations while using only a single FPGA. When six iterations are performed, the decoder operates at an information bit rate greater than 32 kbps. / Master of Science

As technology evolves and new methods for designing radios arise, it becomes necessary to continue the search for fast and flexible development environments. Some of these new technologies include software defined radio (SDR), Field Programmable Gate Arrays (FPGAs), and the open source project GNU Radio. Software defined radio is a concept that GNU Radio has harnessed to allow developers to quickly create flexible radio designs. In terms of hardware, the maturity of FPGAs give radio designers new opportunities to develop high-speed radios having high-throughput and low-latency, yet the conventional build-time for FPGAs is a limiting factor for productivity. Recent research has lead to reductions in build-time by using FPGAs in a non-traditional manner, meaning productivity no longer has to be sacrificed. The AgileHW project demonstrated this concept and will be used as a basis to develop an overlaying architecture that uses a combination of the technologies mentioned to create a flexible, open, and efficient environment for radio development. This thesis discusses the realization of this architecture with the use of Xilinx FPGAs as a hardware accelerator for an enhanced GNU Radio. / Master of Science

This thesis describes the implementation of a system that can generate two types of image pyramids: the Gaussian pyramid and the Laplacian pyramid. These have been developed using the SPLASH II attached processor, which is a reconfigurable platform based on Field Programmable Gate Arrays (FPGA). The design was first modeled in VHDL, and was then simulated and synthesized to a gate list using a SPLASH II simulator and the Synopsys synthesis tool. The gate list was then mapped onto Xilinx XC4010 FPGA architectures. Three complete designs have been developed to generate pyramids on SPLASH II: two for generating the Gaussian pyramid, and one for generating the Laplacian pyramid. One of the designs produces a complete image pyramid within one image frame time of 33 ms. The other two designs produce complete pyramids within two frame times. All three designs can be used as pipeline stages within a larger image processing system. / Master of Science

The Xilinx Partial Reconfiguration tool kits have been instrumental for performing a wide variety of research on Xilinx FPGAs. These tool kits provide a methodology for creating rectangular partial reconfiguration modules that can be swapped in and out of a static baseline design with one or more PR slots. This thesis presents a new PR toolkit called OpenPR that, for starters, provides similar functionality to the Xilinx PR tool kits. The distinguishing feature of this toolkit is that it is being released as open source, and is intended to be customizable to the needs of researchers. OpenPR has been designed to be easy to use, extensible, portable, and compatible with a wide range of Xilinx software and devices. Aside from supporting the slot-based PR paradigm, OpenPR also provides a solid base for further research into partial reconfiguration and FPGA productivity oriented design tools. / Master of Science

This research consists of the design of a low-power, low-cost, nanosatellite computer system solution. The proposed system solution, and design and implementation of a multiple-bus master FPGA and health monitoring space computer subsystem are described. In the fall of 1998, the US Air Force (USAF) funded Virginia Polytechnic Institute & State University (Virginia Tech), The University of Washington (UW), and Utah State University (USU) with $100,000 each to pursue a formation-flying satellite cluster. The program specified that a cluster of three satellites would maintain radio contact through UHF cross-link communication to report relative positions, obtained through GPS, and coordinate scientific measurement mission activities. This satellite cluster, named Ionospheric Observation Nanosatellite Formation (ION-F) is presently scheduled for launch in June of 2003. Maintaining some degree of system reliability in the error-prone space environment was desired for this low-cost space program. By utilizing high-reliability components in key system locations, and monitoring less reliable portions of the computer system for faults, an improvement in overall system reliability was achieved. The development of a one-wire health monitoring bus master was performed. A Synchronous Serial Peripheral Interface (SPI) bus master was utilized to extend the communication capabilities of the CPU. In addition, discrete I/O functions and A/D converter interfaces were developed for system health monitoring and the spacecraft Attitude Determination and Control System (ADCS). / Master of Science

Two research projects are proposed that rely on Tools for open Reconfigurable Computing (TORC) and the openness of the Xilinx tool chain. The first project, the Embedded FPGA Transmitter, relies on the ability to add arbitrary routes to a physical FPGA which serve no obvious purpose. These routes can then mimic an antenna and transmit directly from the FPGA. This mechanism is not supported utilizing standard hardware description languages; however, the Embedded FPGA Transmitter requires measurements on a real FPGA to determine success. The second project is a back-end tools accelerator designed to reduce the compilation time for FPGA times. As the complexity of FPGAs have exceeded over a million logic cells, the compilation problem size has greatly expanded. The open-source project, TORC, provides an excellent framework for new FPGA research that provides physical, real-world results to ensure the applicability of the research. / Master of Science