Prototyping new systems on hardware is a time-consuming task with limited scope for architectural exploration. The aim of this work was to perform fast prototyping of general-purpose graphics processing units (GPGPUs) on field programmable gate arrays (FPGAs) using a novel tool chain. This hardware flow combined with the higher level simulation flow using the same source code allowed us to create a whole tool chain to study and build future architectures using new technologies. It also gave us enough flexibility at different granularities to make architectural decisions. We will also discuss some example systems that were built using this tool chain along with some results.

ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California / Multiple-Input Multiple-Output (MIMO) systems have at least two transmitting antennas, each generating unique signals. However some applications may require three, four, or more transmitting devices to achieve the desired system performance. This paper describes the design of a scalable MIMO transmitter, based on field programmable gate array (FPGA) technology. Each module contains a FPGA, and associated digital-to-analog converters, I/Q modulators, and RF amplifiers needed to power one of the MIMO transmitters. The system was designed to handle up to a 10 Mbps data rate, and transmit signals in the unlicensed 2.4 GHz ISM band.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006. / This thesis investigates to the design, analysis and testing of a Superconducting Programmable Gate Array (SPGA). The objective was to apply existing programmable logic concepts to RSFQ circuits and in the process develop a working prototype of a superconducting programmable logic device. Various programmable logic technologies and architectures were examined and compared to find the best solution. Using Rapid Single Flux Quantum (RSFQ) circuits as building blocks, a complete functional design was assembled incorporating a routing architecture and logic blocks. The Large-Scale Integrated circuit (LSI) layout of the final chip is presented and discussed followed by a discussion on testing. This thesis demonstrates the successful implementation of a fully functional reprogrammable logic device using RSFQ circuitry.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / The availability of high density FPGAs has made the use of soft-core processors an attractive proposition for the low volume space market. Soft-core processors combine the power of programmable logic with the ease of use of a conventional processor to provide a highly customisable solution. However, the SRAM FPGAs used as implementation platform are especially susceptable to radiation induced single event upsets, due to the sensitivity of their configuration memory. To safely use these processors in a space environment requires the modification of the processor to safely mitigate these effects. This thesis presents the process followed to develop and test a fault tolerant implementation of an 8-bit PicoBlaze soft-core processor on a Xilinx Spartan-3 SRAM FPGA. A thorough investigation was made into the available methods that can be used to mitigate single event upsets, in order to identify the most suitable ones. Guidelines for the application of SEU mitigation techniques to SRAM FPGAs were proposed. A single event upset simulator was designed and constructed to compare the different techniques. It mimics SEUs by injecting errors into the configuration memory of an FPGA. The results of error injection were used to develop a PicoBlaze implementation with limited overhead, while it still offers a high degree of error mitigation. Three different designs were tested by proton irradiation to verify the protection afforded by the mitigation techniques. It was found that protected designs were more robust. The cross-section of the FPGA was also determined, which can be used with the SEU simulator to predict the dynamic cross-section of designs. The work contained in this thesis demonstrates the use of open-source intellectual property with commercial-off-the-shelf components to develop a robust component for use in the miniature spacecraft market.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

A Field-Programmable Gate Array (FPGA) is a configurable platform for implementing a variety of logic circuits. It implements a circuit by the means of logic elements, usually Lookup Tables, connected by a programmable routing network. To utilize an FPGA effectively Computer Aided Design (CAD) tools have been developed. These tools implement circuits by using a traditional CAD flow, where the circuit is analyzed, synthesized, technology mapped, and finally placed and routed on the FPGA fabric. This flow, while generally effective, can produce sub-optimal results because once a stage of the flow is completed it is not revisited. This problem is addressed by an enhanced flow known Physical Synthesis, which consists of a set of iterations of the traditional flow with one key difference: the result of each iteration directly affects the result of the following iteration. An optimization can therefore be evaluated and then adjusted as needed in the following iterations, resulting in an overall better implementation. This CAD flow is challenging to work with because for a given FPGA researchers require access to each stage of the flow in an iterative fashion. This is particularly challenging when targeting modern commercial FPGAs, which are far more complex than a simple Lookup Table and Flip-Flop model generally used by the academic community. This dissertation describes a unified framework, called the Physical Synthesis Toolkit (PST), for research and development of optimizations for modern FPGA devices. PST provides access to modern FPGA devices and CAD tool flow to facilitate research. At the same time the amount of effort required to adapt the framework to a new FPGA device is kept to a minimum. To demonstrate that PST is an effective research platform, this dissertation describes optimization and modeling techniques that were implemented inside of it. The optimizations include: an area reduction technique for XOR-based logic circuits implemented on a 4-LUT based FPGA (25.3% area reduction), and a dynamic power reduction technique that reduces glitches in a circuit implemented on an Altera Stratix II FPGA (7% dynamic power reduction). The modeling technique is a novel toggle rate estimation approach based on the XOR-based decomposition, which reduces the estimate error by 37% as compared to the latest release of the Altera Quartus II CAD tool.

Leong Monk Ping. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (p. 255-278). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

by Xue-jie Zhang. / "December 1999." / Thesis (Ph.D.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (p. 144-[152]). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Field Programmable Gate Array (FPGA) has a dominating market in digital system prototyping and reconfigurable computing. To make a flexible and efficient FPGA chip both the hardware architecture and the design tool should be further engineered. An innovative architecture always requires excellent development of EDA tools to fully explore the intrinsic merits of the hardware. / FPGA Technology Mapping is an important design automation problem which affects placement and routing dramatically. Depth-optimal technology mapping algorithms were proposed and produced quality mapping solution for delay minimization. However such algorithms have not yet considered to further reduce area consumption using the powerful logic transformation techniques. / On hardware side, we present a study on the effect of direct and fast routing hard-wires in FPGA routing architecture. Based on the routing pattern analyzed from real routing data, we proposed a so-called shortcut -based routing to handle short and localized routing requirements. Experimental results show that the shortcuts are well utilized and it allows a better average wirelength usage in the whole routing architecture. / On software side, we propose a versatile approach to combine logic transformation and technology mapping. In addition to a level-reduction scheme, we also present a method of reducing the number of LUTs used while keeping the depth optimality. Our approach is based on a greedy but effective heuristic to choose good alternative wires for transformation. Large number of experiments were conducted to analyze the effectiveness of the system. Our results show that our approach can effectively reduce at least 5% (up to 25%) of the area over initial mapping by various state-of-the-art FPGA technology mappers. Furthermore, we found that the delay performance can be improved by 5% when the area is reduced by our system. / Tang, Wai Chung. / Adviser: David Yu-Liang Wu. / Source: Dissertation Abstracts International, Volume: 70-06, Section: B, page: 3704. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 70-74). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Cheung Yu Hoi Ocean. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 65-70). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims --- p.2 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Thesis Outline --- p.3 / Chapter 2 --- Virtual Private Network and FreeS/WAN --- p.4 / Chapter 2.1 --- Introduction --- p.4 / Chapter 2.2 --- Internet Protocol Security (IPSec) --- p.4 / Chapter 2.3 --- Secure Virtual Private Network --- p.6 / Chapter 2.4 --- LibDES --- p.9 / Chapter 2.5 --- FreeS/WAN --- p.9 / Chapter 2.6 --- Commercial VPN solutions --- p.9 / Chapter 2.7 --- Summary --- p.11 / Chapter 3 --- Cryptography and Field-Programmable Gate Arrays (FPGAs) --- p.12 / Chapter 3.1 --- Introduction --- p.12 / Chapter 3.2 --- The Data Encryption Standard Algorithm (DES) --- p.12 / Chapter 3.2.1 --- The Triple-DES Algorithm (3DES) --- p.14 / Chapter 3.2.2 --- Previous work on DES and Triple-DES --- p.16 / Chapter 3.3 --- The IDEA Algorithm --- p.17 / Chapter 3.3.1 --- Multiplication Modulo 2n + 1 --- p.20 / Chapter 3.3.2 --- Previous work on IDEA --- p.21 / Chapter 3.4 --- Block Cipher Modes of operation --- p.23 / Chapter 3.4.1 --- Electronic Code Book (ECB) mode --- p.23 / Chapter 3.4.2 --- Cipher-block Chaining (CBC) mode --- p.25 / Chapter 3.5 --- Field-Programmable Gate Arrays --- p.27 / Chapter 3.5.1 --- Xilinx Virtex-E´ёØ FPGA --- p.27 / Chapter 3.6 --- Pilchard --- p.30 / Chapter 3.6.1 --- Memory Cache Control Mode --- p.31 / Chapter 3.7 --- Electronic Design Automation Tools --- p.32 / Chapter 3.8 --- Summary --- p.33 / Chapter 4 --- Implementation / Chapter 4.1 --- Introduction --- p.36 / Chapter 4.1.1 --- Hardware Platform --- p.36 / Chapter 4.1.2 --- Reconfigurable Hardware Computing Environment --- p.36 / Chapter 4.1.3 --- Pilchard Software --- p.38 / Chapter 4.2 --- DES in ECB mode --- p.39 / Chapter 4.2.1 --- Hardware --- p.39 / Chapter 4.2.2 --- Software Interface --- p.40 / Chapter 4.3 --- DES in CBC mode --- p.42 / Chapter 4.3.1 --- Hardware --- p.42 / Chapter 4.3.2 --- Software Interface --- p.42 / Chapter 4.4 --- Triple-DES in CBC mode --- p.45 / Chapter 4.4.1 --- Hardware --- p.45 / Chapter 4.4.2 --- Software Interface --- p.45 / Chapter 4.5 --- IDEA in ECB mode --- p.48 / Chapter 4.5.1 --- Multiplication Modulo 216 + 1 --- p.48 / Chapter 4.5.2 --- Hardware --- p.48 / Chapter 4.5.3 --- Software Interface --- p.50 / Chapter 4.6 --- Triple-DES accelerator in LibDES --- p.51 / Chapter 4.7 --- Triple-DES accelerator in FreeS/WAN --- p.52 / Chapter 4.8 --- IDEA accelerator in FreeS/WAN --- p.53 / Chapter 4.9 --- Summary --- p.54 / Chapter 5 --- Results --- p.55 / Chapter 5.1 --- Introduction --- p.55 / Chapter 5.2 --- Benchmarking environment --- p.55 / Chapter 5.3 --- Performance of Triple-DES and IDEA accelerator --- p.56 / Chapter 5.3.1 --- Performance of Triple-DES core --- p.55 / Chapter 5.3.2 --- Performance of IDEA core --- p.58 / Chapter 5.4 --- Benchmark of FreeSAVAN --- p.59 / Chapter 5.4.1 --- Triple-DES --- p.59 / Chapter 5.4.2 --- IDEA --- p.60 / Chapter 5.5 --- Summary --- p.61 / Chapter 6 --- Conclusion --- p.62 / Chapter 6.1 --- Future development --- p.63 / Bibliography --- p.65