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FPGA implementation of low density parity check codes decoderVijayakumar, Suresh. Mikler, Armin, January 2009 (has links)
Thesis (M.S.)--University of North Texas, August, 2009. / Title from title page display. Includes bibliographical references.
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Design and implementation of a multithreaded softcore processor with tightly coupled hardware real-time operating systemWijesinghe, Terance Prabhasara. January 1900 (has links)
Thesis (M.S.)--West Virginia University, 2008. / Title from document title page. Document formatted into pages; contains ix, 107 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 101-107).
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CAD algorithms for field programmable logic devices /Lee, Kok Kiong, January 2000 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 134-144). Available also in a digital version from Dissertation Abstracts.
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Charge-based analog circuits for reconfigurable smart sensory systemsPeng, Sheng-Yu. January 2008 (has links)
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Degertekin, F.; Committee Member: Ghovanloo, Maysam; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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High performance embedded reconfigurable computing: data security and media processing applicationsKwok, Tai-on, Tyrone., 郭泰安. January 2005 (has links)
published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy
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Exploration of alternatives to general-purpose computers in neural simulationGraas, Estelle Laure 08 1900 (has links)
No description available.
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A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAsLuu, Jason 27 July 2010 (has links)
The complexity of Field-Programmable Gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement combinational logic and the fixed-function hard blocks contain complex interconnects, hierarchy and modes. The goal of this thesis is to both support that complexity and enable future architecture exploration of even increased complexity and new kinds of hard functionality. To accomplish this, a Computer-Aided Design (CAD) flow that can map a user circuit to an FPGA with these complex blocks is needed. We propose a new language that can describe these complex blocks and a new area-driven tool for the packing stage of that CAD flow. The packing stage groups components of a user circuit into the complex blocks available on the FPGA. We conduct experiments to illustrate the quality of the packing tool and to demonstrate the newly-enabled architecture exploration capabilities.
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Physical Synthesis Toolkit for Area and Power Optimization on FPGAsCzajkowski, Tomasz Sebastian 19 January 2009 (has links)
A Field-Programmable Gate Array (FPGA) is a configurable platform for implementing a variety of logic circuits. It implements a circuit by the means of logic elements, usually Lookup Tables, connected by a programmable routing network. To utilize an FPGA effectively Computer Aided Design (CAD) tools have been developed. These tools implement circuits by using a traditional CAD flow, where the circuit is analyzed, synthesized, technology mapped, and finally placed and routed on the FPGA fabric. This flow, while generally effective, can produce sub-optimal results because once a stage of the flow is completed it is not revisited.
This problem is addressed by an enhanced flow known Physical Synthesis, which consists of a set of iterations of the traditional flow with one key difference: the result of each iteration directly affects the result of the following iteration. An optimization can therefore be evaluated and then adjusted as needed in the following iterations, resulting in an overall better implementation. This CAD flow is challenging to work with because for a given FPGA researchers require access to each stage of the flow in an iterative fashion. This is particularly challenging when targeting modern commercial FPGAs, which are far more complex than a simple Lookup Table and Flip-Flop model generally used by the academic community.
This dissertation describes a unified framework, called the Physical Synthesis Toolkit (PST), for research and development of optimizations for modern FPGA devices. PST provides access to modern FPGA devices and CAD tool flow to facilitate research. At the same time the amount of effort required to adapt the framework to a new FPGA device is kept to a minimum.
To demonstrate that PST is an effective research platform, this dissertation describes optimization and modeling techniques that were implemented inside of it. The optimizations include: an area reduction technique for XOR-based logic circuits implemented on a 4-LUT based FPGA (25.3% area reduction), and a dynamic power reduction technique that reduces glitches in a circuit implemented on an Altera Stratix II FPGA (7% dynamic power reduction). The modeling technique is a novel toggle rate estimation approach based on the XOR-based decomposition, which reduces the estimate error by 37% as compared to the latest release of the Altera Quartus II CAD tool.
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A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAsLuu, Jason 27 July 2010 (has links)
The complexity of Field-Programmable Gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement combinational logic and the fixed-function hard blocks contain complex interconnects, hierarchy and modes. The goal of this thesis is to both support that complexity and enable future architecture exploration of even increased complexity and new kinds of hard functionality. To accomplish this, a Computer-Aided Design (CAD) flow that can map a user circuit to an FPGA with these complex blocks is needed. We propose a new language that can describe these complex blocks and a new area-driven tool for the packing stage of that CAD flow. The packing stage groups components of a user circuit into the complex blocks available on the FPGA. We conduct experiments to illustrate the quality of the packing tool and to demonstrate the newly-enabled architecture exploration capabilities.
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Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAsRavishankar, Chirag January 2012 (has links)
Guarded evaluation is a power reduction technique that involves
identifying sub-circuits (within a larger circuit) whose inputs can be
held constant (guarded) at specific times during circuit operation,
thereby reducing switching activity and lowering dynamic power. The
concept is rooted in the property that under certain conditions, some
signals within digital designs are not "observable" at design
outputs, making the circuitry that generates such signals a candidate
for guarding.
Guarded evaluation has been demonstrated successfully
for custom ASICs; in this work, we apply the technique to FPGAs. In
ASICs, guarded evaluation entails adding additional hardware to the
design, increasing silicon area and cost. Here, we apply the technique
in a way that imposes minimal area overhead by leveraging existing
unused circuitry within the FPGA. The LUT functionality is modified
to incorporate the guards and reduce toggle rates.
The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's
inputs can be held constant without impacting the larger
circuit's functional correctness. We propose a simple solution to
this problem based on discovering gating inputs using "non-inverting paths"
and trimming inputs using "partial non-inverting paths" in the
circuit's AND-Inverter graph representation.
Experimental results show that guarded evaluation can reduce switching activity by
as much as 32% for FPGAs with 6-LUT architectures and 25% for 4-LUT architectures, on
average, and can reduce power consumption in the FPGA interconnect by
29% for 6-LUTs and 27% for 4-LUTs. A clustered architecture with four LUTs to a cluster
and ten LUTs to a cluster produced the best power reduction results.
We implement guarded evaluation at various stages of the FPGA CAD flow and analyze the reductions. We implement
the algorithm as post technology mapping, post packing and post placement optimizations. Guarded Evaluation
as a post technology mapping algorithm inserted the most number of guards and hence achieved the highest activity
and interconnect reduction. However, guarding signals come with a cost of increased fanout and stress on routing
resources. Packing and placement provides the algorithm with additional information of the circuit which is leveraged
to insert high quality guards with minimal impact on routing. Experimental results show that post-packing
and post-placement methods have comparable reductions to post-mapping with considerably lesser impact on the critical
path delay and routability of the circuit.
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