Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2005. / Includes bibliographical references (p. 105-108).

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (M. Phil.)--University of Hong Kong, 2005. / Title proper from title frame. Also available in printed format.

Thesis (M.S.)--Ohio University, June, 2004. / Title from PDF t.p. Includes bibliographical references (p. 99-100)

Thesis (M.S.)--Ohio University, August, 2004. / Title from PDF t.p. Includes bibliographical references (p. 135-139)

Thesis (M.S.)--University of North Texas, May, 2007. / Title from title page display. Includes bibliographical references.

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (p. 75-86).

Field-Programmable Gate Arrays (FPGAs) são largamente utilizadas em sistemas digitais por características como flexibilidade, baixo custo e alta densidade. Estas características advém do uso de células de SRAM na memória de configuração, o que torna estes dispositivos suscetíveis a erros induzidos por radiação, tais como SEUs. TMR é o método de mitigação mais utilizado, no entanto, possui um elevado custo tanto em área como em energia, restringindo seu uso em aplicações de baixo custo e/ou baixo consumo. Como alternativa a TMR, propõe-se utilizar DMR associado a um mecanismo de reparo da memória de configuração da FPGA chamado scrubbing. O reparo de FPGAs em sistemas em tempo real apresenta desafios específicos. Além da garantia da computação correta dos dados, esta computação deve se dar completamente dentro do tempo disponível (time-slot), devendo ser finalizada antes do tempo limite (deadline). A diferença entre o tempo de computação dos dados e a deadline é chamado de slack e é o tempo disponível para reparo do sistema. Este trabalho faz uso de scrubbing deslocado dinâmico, que busca maximizar a probabilidade de reparo da memória de configuração de FPGAs dentro do slack disponível, baseado em um diagnóstico do erro. O scrubbing deslocado já foi utilizado com técnicas de diagnóstico de grão fino (NAZAR, 2015). Este trabalho propõe o uso de técnicas de diagnóstico de grão grosso para o scrubbing deslocado, evitando as penalidades de desempenho e custos em área associados a técnicas de grão fino. Circuitos do conjunto MCNC foram protegidos com as técnicas propostas e submetidos a seções de injeção de erros (NAZAR; CARRO, 2012a). Os dados obtidos foram analisados e foram calculadas as melhores posição iniciais do scrubbing para cada um dos circuitos. Calculou-se a taxa de Failure-in-Time (FIT) para comparação entre as diferentes técnicas de diagnóstico propostas. Os resultados obtidos confirmaram a hipótese inicial deste trabalho que a redução do número de bits sensíveis e uma baixa degradação do período do ciclo de relógio permitiram reduzir a taxa de FIT quando comparadas com técnicas de grão fino. Por fim, uma comparação entre as três técnicas propostas é feita, analisando o desempenho e custos em área associados a cada uma. / Field-Programmable Gate Arrays (FPGAs) are widely used in digital systems due to characteristics such as flexibility, low cost and high density. These characteristics are due to the use of SRAM memory cells in the configuration memory, which make these devices susceptible to radiation-induced errors, such as SEUs. TMR is the most used mitigation technique, but it has an elevated cost both in area as well as in energy, restricting its use in low cost/low energy applications. As an alternative to TMR, we propose the use of DMR associated with a repair mechanism of the FPGA configuration memory called scrubbing. The repair of FPGA in real-time systems present a specific set of challenges. Besides guaranteeing the correct computation of data, this computation must be completely carried out within the available time (time-slot), being finalized before a time limit (deadline). The difference between the computation time and the deadline is called the slack and is the time available to repair the system. This work uses a dynamic shifted scrubbing that aims to maximize the repair probability of the configuration memory of the FPGA within the available slack based on error diagnostic. The shifted scrubbing was already proposed with fine-grained diagnostic techniques (NAZAR, 2015). This work proposes the use of coarse-grained diagnostic technique as a way to avoid the performance penalties and area costs associated to fine-grained techniques. Circuits of the MCNC suite were protected by the proposed techniques and subject to error-injection campaigns (NAZAR; CARRO, 2012a). The obtained data was analyzed and the best scrubbing starting positions for each circuit were calculated. The Failure-in-Time (FIT) rates were calculated to compare the different proposed diagnostic techniques. The obtained results validated the initial hypothesis of this work that the reduction of the number of sensitive bits and a low degradation of the clock cycle allowed a reduced FIT rate when compared with fine-grained diagnostic techniques. Finally, a comparison is made between the proposed techniques, considering performance and area costs associated to each one.

Thesis submitted in fulfilment of the requirements for the degree Magister Technologiae: Discipline Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology 2008 / As one of the biggest developing country in the world, South Africa is developing very fast resent years. The country’s industrialization process is rapidly evolved. The manufacturing industry as one of the most important sections of the industrialization is playing a very heavy role in South Africa’s economic growth. Big percentage of population is involved in the manufacturing industry. It is necessary to keep and enhance the competitiveness of the South Africa’s manufacturing industry in the world wide. But the manufacturing companies are facing with unpredictable market demands and global competitions. To overcome these challenges, the manufacturing companies need to produce new products which can cater to the market demand as soon as possible. Reconfigurable Manufacturing System (RMS) is one of the possible solutions for the manufacturing companies to produce the suitable product for the market in a short period of time with low cost and flexibility. That is because the RMS can be reconfigured easily according to the required specifications for manufacturing the appropriate product for the market and with above mentioned characteristics. Now, RMS is considered as one of the promising concepts for mass production. As one of the very latest research fields, many companies, universities and institutions have been involved to design and develop RMSs. South Africa as one of the most important manufacturing country in the world, her own universities and researchers has the obligation to study this field and follow the newest development steps. In this project, a lab-scaled reconfigurable plant and a Field Programmable Gate Array (FPGA) technology based reconfigurable controller are used to realize and verify the concepts of the RMS in order to find the methodology of developing RMSs. The lab-scaled reconfigurable plant can be reconfigured into the inverted pendulum and the overhead crane. Although it is not used for manufacturing purpose, it can be used to verify the RMS concepts and the control strategies applied to it. Furthermore, control of the inverted pendulum and the overhead crane are both typical problems in the control field. It is meaningful to develop the controllers for them. As the reconfigurable plant is configured, the reconfigurable controller is reconfigured synchronously in order to produce the proper control signal for the reconfigured plant. In this project, both linear and nonlinear control strategies are deployed. Good results are received. The outcomes of the project are mainly for the education and fundamental research purposes, but the developed control strategies have significant sense towards the military missile guidance and the overhead crane operation in industry.

Thesis is submitted in fulfilment of the requirements for the degree Master of Technology: Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology 2013 / The CubeSat standard has various engineering challenges due to its small size and surface area. The challenge is to incorporate a large amount of technology into a form factor no bigger than 10cm3. This research project investigates the space environment, solar cells, secondary sources of power, and Field-Programmable-Gate-Array (FPGA) technology in order to address the size, weight and power challenges presented by the CubeSat standard. As FPGAs have not yet been utilised in this particular sub-system as the main controller, this research investigates whether or not the implementation of an FPGA-based electronic power supply sub-system will optimise its functionality by overcoming these size weight and power challenges. The SmartFusion FPGA was chosen due to its analogue front end which can reduce the number of peripheral components required by such complex systems. Various maximum power point tracking algorithms were studied and it was determined that the perturb-and-observe maximum power point tracking algorithm best suits the design constraints, as it only requires the measurement of either solar cell voltage or solar cell current, thus further decreasing the component count. The SmartFusion FPGA analogue compute engine allows for increased performance of the perturb-and-observe algorithm implemented on the microcontroller sub-system as it allows for the offloading of many repetitive calculations. A VHDL implementation of the pulse-width-modulator was developed in order to produce the various changes in duty cycle produced by the perturb-and-observe algorithm. The aim of this research project was achieved through the development and testing of a nano-satellite power system prototype using the SmartFusion FPGA from Microsemi with a decreased number of peripheral circuits. Maximum power point was achieved in 347ms at worst case with a 55% decrease in power consumption from the estimated 330mW as indicated in the power budget. The SmartFusion FPGA consumes only a worst case of 148.93mW. It was found that the unique features of the SmartFusion FPGA do in fact address the size weight and power constraints of the CubeSat standard within this sub-system.