As VLSI circuits continue to have more and more transistors over time, the question of not only how to use, but how to manage the complexity of so many transistors becomes increasingly important. Four hypothesis are given for the design of a system that scales-up as transistors continue to shrink. An architecture is presented that satisfies these hypothesis, and the motivation behind the hypothesis is further explained. The use of this architecture's unique features to implement an efficient, defect-tolerant parallel bootstrap system is discussed. A detailed methodology for implementing this system in vivo is described. A sample problem--simulation of heat flow--is presented, and its solution using the proposed architecture is described in detail. A comparison is made between the proposed architecture and a set of contemporary architectures, and the former is shown to have desirable performance in a number of areas. Conclusion are given, and plans for future work are presented. / Ph. D.

A large body of work has been produced in the area of productivity enhancers for the design of both Software-Defined Radio and Field Programmable Gate Arrays systems. These tool are created with the goal of aiding the user in the process of instantiating a design. They do not address, however, a specific use-case in which the user does not know or care about what the design of his system is. In this work, analysis-based design is presented and applied to FPGA-based SDRs. The RapidRadio framework abstracts away much of the knowledge required for analyzing an unknown signal and building an FPGA-based receiver. Resource utilization is traded-off for reduced implementation time and increased exibility. Automatic modulation classification is done with blind parameter estimation. Unlike other contemporary work, no a priori knowledge about the signal being classified is assumed. This leads to the development of a system that does not depend on perfect synchronization to classify the signal. A new quasi-generic synchronization architecture that allows the synchronization of multiple modulations schemes is presented. The result of the modulation classification is used to automatically create an FPGA-based radio receiver. / Ph. D.

Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs. The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated with the same arbitrary test data on the same framework as the hardware. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA. / Ph. D.

Today's Field Programmable Gate Array (FPGA) research community could use an extensible tool flow enabling designers to examine new algorithms and new methods of interacting with FPGA configurations. One such flow is JHDLBits, which integrates two prominent FPGA design environments: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits with the high-level structural circuit design of JHDL. Furthermore, the JHDLBits flow provides greater control of resource manipulation, placement, and routing, and gives researchers a sandbox to explore advanced interactions with FPGA configurations. This thesis presents the overall architecture of the open-source JHDLBits project. Details are provided on how the core components -- JHDL, JBits3 for Virtex-II, the ADB connectivity database, and VTsim, a Virtex-II device simulator -- are linked together to provide an integrated design environment. Strategies and philosophies of the open source movement are also examined to successfully establish the support for and involvement of the FPGA research community throughout the JHDLBits open source endeavor. / Master of Science

The security of a radio system hinges on its ability to effectively authenticate a user. This work proposes a two-factor authentication scheme using a token and a biometric. The users' access rights are determined during authentication and the users are served only those channels of data that they are privileged to receive. The strengths and the weaknesses of the implementation in reconfigurable hardware are identified. The capabilities of the scheme are put into perspective by comparing it to a high-end authentication system and by evaluating the use of standardized APIs and low-end authentication devices. Modifications to the system are suggested to improve the level of security the scheme provides. Finally, a baseline study is carried out to measure the data processing performance of a radio developed in reconfigurable hardware, which uses the proposed authentication scheme. / Master of Science

A wide variety of design security strategies have been developed for programmable logic devices, but less work has been done to determine which are optimal for any given design and any given security goal. To address this, we consider not only metrics related to the performance of the design security practice, but also the likely action of an adversary given their goals. We concern ourselves principally with adversaries attempting to make use of hardware Trojans, although we also show that our work can be generalized to adversaries and defenders using any of a variety of microelectronics exploitation and defense strategies. Trojans are inserted by an adversary in order to accomplish an end. This goal must be considered and quantified in order to predict the adversary's likely action. Our work here builds upon a security economic approach that models the adversary and defender motives and goals in the context of empirically derived countermeasure efficacy metrics. The approach supports formation of a two-player strategic game to determine optimal strategy selection for both adversary and defender. A game may be played in a variety of contexts, including consideration of the entire design lifecycle or only a step in product development. As a demonstration of the practicality of this approach, we present an experiment that derives efficacy metrics from a set of countermeasures (defender strategies) when tested against a taxonomy of Trojans (adversary strategies). We further present a software framework, GameRunner, that automates not only the solution to the game but also enables mathematical and graphical exploration of "what if" scenarios in the context of the game. GameRunner can also issue "prescriptions," sets of commands that allow the defender to automate the application of the optimal defender strategy to their circuit of concern. We also present how this work can be extended to adjacent security domains. Finally, we include a discussion of future work to include additional software, a more advanced experimental framework, and the application of irrationality models to account for players who make subrational decisions. / Doctor of Philosophy / We present a security economic model that informs the optimal selection of programmable logic design security strategies. Our model accurately represents the economics and effectiveness of available design security strategies and accounts for the varieties of available exploits. Paired with game theoretic analysis, this model informs microelectronics designers and associated policy makers of optimal defensive strategies. Treating the adversary and defender as opponents in a two-player game, our security economic model tells us how either player will play if it is known in advance how their opponent plays. The additional use of game theory allows us to determine the optimal play of both players simultaneously without prior knowledge other than models of players beliefs.

Multiple research projects are proposed that utilize low-level knowledge of Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) design processes to enable additional research avenues. In order to accomplish these projects, Tools for Open Reconfigurable Computing (TORC) is utilized to provide a robust environment for circuit analysis and modifications. These projects rely on looking at the low-level constructs of the internals of these microchips. Through this knowledge, techniques for performing supply chain evaluations are proposed utilizing a non-binary comparison of multiple characteristic vectors between different FPGA manufacturing lots, and FPGAs that have been exposed to different environmental conditions. Second, techniques are proposed that look at design recovery by performing fuzzy segmentation and fuzzy matching algorithms to a problem area that has traditionally focused on exact graph sub-isomorphism solutions. Through these projects, additional research vectors are opened to protect and analyze the engineering efforts that are exerted in the design of FPGA and ASIC projects. / Ph. D.

Computer vision technology can be seen in a variety of applications ranging from mobile phones to autonomous vehicles. Many computer vision applications such as drones and autonomous vehicles requires real-time processing capability in order to communicate with the control unit for sending commands in real time. Besides real-time processing capability, it is crucial to keep the power consumption low in order to extend the battery life of not only mobile devices, but also drones and autonomous vehicles. FPGAs are desired platforms that can provide high-performance and low-power solutions for real-time video processing. As hardware designs typically are more time consuming than equivalent software designs, this thesis proposes a rapid prototyping flow for FPGA-based video processing system design by taking advantage of the use of high performance AXI interface and a high level synthesis tool, Vivado HLS. Vivado HLS provides the convenience of automatically synthesizing a software implementation to hardware implementation. But the tool is far from being perfect, and users still need embedded hardware knowledge and experience in order to accomplish a successful design. In order to effectively create a stream type video processing system as well as to utilize the fastest memory on an FPGA, a sliding window memory architecture is proposed. This memory architecture can be applied to a series of video processing algorithms while the latency between an input pixel and an output pixel is minimized. By comparing my approach with other works, this optimized memory architecture proves to offer better performance and lower resource usage over what other works could offer. Its reconfigurability also provides better adaptability of other algorithms. In addition, this work includes performance and power analysis among an Intel CPU based design, an ARM based design, and an FPGA-based embedded design. / Master of Science

Traditional hardware radios provide very rigid solutions to radio problems. Intelligent software defined radios, also known as cognitive radios, provide flexibility and agility compared to hardware radio systems. Cognitive radios are well suited for radio applications in a changing radio frequency environment, such as dynamic spectrum access. In this thesis, a cognitive radio is demonstrated where the system self reconfigures to demodulate a detected waveform. The GNU Radio framework is used to provide basic software defined radio building blocks and is supplemented with FPGA accelerators. The use of GNU Radio compliant hardware interfaces allows for seamless hardware/software radio deployments. Dynamic resource mapping allows radio designers to operate at a layer of abstraction above the physical radio implementation. By establishing lower level abstraction layers, future researchers can focus on larger picture concepts such as learning algorithms and behavioral models for the cognitive engine. / Master of Science

As Field Programmable Gate Arrays (FPGAs) continue to become integral parts of embedded systems, it is imperative to consider their security. While much of the research in this field is oriented toward the protection of the intellectual property contained in the FPGA's configuration, the protection of the design's integrity from malicious attack against the configuration is critical to the operation of the system. Methods for attacking the configuration are semi-invasive attacks, such as fault injection, and data tampering of incoming partial bitstreams. This thesis introduces methods for securing the integrity of an FPGA's configuration. The design and implementation is discussed for a system that consists of three parts. The first subsystem monitors the running configuration. The second subsystem authenticates partial bistreams that may be used for repairing the configuration from malicious alterations during run-time. The third subsystem indicates if the system itself succumbs to a malicious attack. The system is implemented on-chip, allowing the FPGA to effectively secure itself from attack. / Master of Science