Embedded systems are becoming nearly ubiquitous, found in a plurality of devices ranging from everyday cars and dishwashers to sophisticated spy satellites and remote sensing equipment. As the applications for embedded systems increase in number and diversity and continue to pervade our lives, a need arises to secure these systems. Whether the need arises from a desire to protect personal, proprietary, sensitive, or classified information, the security of the embedded system seeks to maintain the confidentiality and integrity of data contained within the system. Research into securing embedded systems is in its nascent stages. The generally accepted methodology of securing embedded systems involves techniques that either modify an embedded system's processor or entail custom ASIC hardware. This thesis presents a novel embedded system architecture for secure software processing that does not involve processor modification, but rather processor augmentation to ensure the confidentiality and integrity of information contained within the embedded system. Specifically, configurable logic placed at the processor periphery provides just-in-time cryptographic transformation of instructions, data, and I/O of a running embedded application. In addition to presenting the embedded secure software platform, this thesis provides a characterization of the data protection architecture of the platform. / Master of Science

The JBits Application Programming Interface has significantly shortened FPGA reconfiguration times by manipulating the configurable resources of the FPGAs directly under software control. The execution of JBits programs, however, requires a Java Virtual Machine to be implemented on the platform where the configurations will be modified. This presents a problem for embedded systems where a microprocessor to run a Java Virtual Machine may not be available or desirable. This thesis discusses the implementation of a FPGA platform that allows the execution of JBits programs, effectively changing the configuration of a FPGA within a FPGA. This thesis also presents a four step developing and testing strategy for JBits programs that are intended to run on this FPGA platform. / Master of Science

In this thesis, we present a versatile parallel programming model composed of an individual general-purpose processor aided by several application-specific coprocessors. These computing units operate under a simplification of the master-worker model. The user-defined coprocessors may be either homogeneous or heterogeneous. We analyze system performance with regard to system size and task granularity, and we present experimental results to determine the optimal operating conditions. Finally, we consider the suitability of this approach for scientific simulations — specifically for use in agent-based models of biological systems. / Master of Science

No description available.

Image registration is the process of relating the intensity values of one image to another image using their pixel c~?tent alone. An example use of this technique is to create panoramas from individual images taken froin a rotating camera. A class of image registration algorithms, known as direct registration methods, uses intensity derivatives to iteratively estimate the parameters modeling the transformation between the images. Direct methods are known for their sub-pixel accurate results; however, their execution is computationally expensive, often times preventing use in an embedded capacity like those encountered in small UIUllann~d aerial vehicle or mobile phone applications. In this work, a high performance FPGA-based direct affine image registration core is presented. The proposed method combines two features: a fully pipelined architecture to compute the linear system of equations, and a Gaussian elimination module, implemented as a finite state machine, to solve the resulting linear system. The design is implemented on a Xilinx ML506 development board featuring a Virtex-5 SX50 FPGA, zero bus turn-around (ZBT) RAM, and VGA input. Experimentation is performed on both real and synthetic data. The registration core performs in excess of 80 frames per second on 640x480 images using one registration iteration.

Field Programmable Gate Arrays (FPGAs) offer a new opportunity for computer vision algorithms. By implementing in Very High Speed Integrated Circuit Hardware Description languate (VHDL), algorithms can be developed quickly, while being running much faster than by using conventional Von Neumann machines (such as a Personal Computer or Macintosh). The process of creating a working design from an algorithm is described in detail, and we present experimental results obtained from such a process for Sobel edge detection, as well as modifications for techniques for background modeling and fire detection.

Thesis (PhD (Electric and Electronic Engineering))--University of Stellenbosch, 2007. / There is increasing use of commercial components in space technology and it is important to recognize that the space radiation environment poses the risk of permanent malfunction due to radiation. Therefore, the integrated circuits used for spacecraft electronics must be resistant to radiation. The effect of using the MOSFET device in a radiation environment is that the gate oxide becomes ionized by the dose it absorbs due to the radiation induced trapped charges in the gate-oxide. The trapped charges in the gate-oxide generate additional space charge fields at the oxide-substrate interface. After a sufficient dose, a large positive charge builds up, having the same effect as if a positive voltage was applied to the gate terminal. Therefore, the transistor source to drain current can no longer be controlled by the gate terminal and the device remains on permanently resulting in device failure. There are four processes involved in the radiation response of MOS devices. First, the ionizing radiation acts with the gate oxide layer to produce electron-hole pairs. Some fraction of the electron-hole pairs recombine depending on the type of incident particle and the applied gate to substrate voltage, i.e. the electric field. The mobility of the electron is orders of magnitude larger than that of the holes in the gate oxide, and is swept away very quickly in the direction of the gate terminal. The time for the electrons to be swept away is on the order of 1ps. The holes that escape recombination remain near their point of origin. The number of these surviving holes determines the initial response of the device after a short pulse of radiation. The cause of the first process, i.e. the presence of the electric field, is the main motivation for design method described in this dissertation. The second process is the slow transport of holes toward the oxide-silicon interface due to the presence of the electric field. When the holes reach the interface, process 3, they become captured in long term trapping sites and this is the main cause of the permanent threshold voltage shift in MOS devices. The fourth process is the buildup of interface states in the substrate near the interface The main contribution of this dissertation is the development of the novel Switched Modular Redundancy (SMR) method for mitigating the effects of space radiation on satellite electronics. The overall idea of the SMR method is as follows: A charged particle is accelerated in the presence of an electric field. However, in a solid, electrons will move around randomly in the absence of an applied electric field. Therefore if one averages the movement over time there will be no overall motion of charge carriers in any particular direction. On applying an electric field charge carriers will on average move in a direction aligned with the electric field, with positive charge carriers such as holes moving in the direction of field, and negative charge carriers moving in the opposite direction. As is the case with process one and two above. It is proposed in this dissertation that if we apply the flatband voltage (normaly a zero bias for the ideal NMOS transistor) to the gate terminal of a MOS transistor in the presence of ionizing radiation, i.e. no electric field across the gate oxide, both the free electrons and holes will on average remain near their point of origin, and therefore have a greater probability of recombination. Thus, the threshold voltage shift in MOS devices will be less severe for the gate terminal in an unbiased condition. The flatband conditions for the real MOS transistor is discussed in appendix E. It was further proposed that by adding redundancy and applying a resting policy, one can significantly prolong the useful life of MOS components in space. The fact that the rate of the threshold voltage shift in MOS devices is dependant on the bias voltage applied to the gate terminal is a very important phenomenon that can be exploited, since we have direct control and access to the voltage applied to the gate terminal. If for example, two identical gates were under the influence of radiation and the gate voltage is alternated between the two, then the two gates should be able to withstand more total dose radiation than using only one gate. This redundancy could be used in a circuit to mitigate for total ionizing dose. The SMR methodology would be to duplicate each gate in a circuit, then selectively only activating one gate at a time allowing the other to anneal during its off cycle. The SMR algorithm was code in the “C” language. In the proposed design methodology, the design engineer need not be concerned about radiation effects when describing the hardware implementation in a hardware description language. Instead, the design engineer makes use of conventional design techniques. When the design is complete, it is synthesized to obtain the gate level netlist in edif format. The edif netlist is converted to structural VHDL code during synthesis. The structural VHDL netlist is fed into the SMR “C” algorithm to obtain the identical redundant circuit components. The resultant file is also a structural VHDL netlist. The generated VHDL netlist or SMR circuit can then be mapped to a Field Programmable Gate Array (FPGA). Spacecraft electronic designers increasingly demand high performance microprocessors and FPGAs, because of their high performance and flexibility. Because FPGAs are reprogrammable, they offer the additional benefits of allowing on-orbit design changes. Data can be sent after launch to correct errors or to improve system performance. System including FPGAs covers a wide range of space applications, and consequently, they are the object of this study in order to implement and test the SMR algorithm. We apply the principles of reconfigurable computing to implement the Switched Modular Redundancy Algorithm in order to mitigate for Total Ionizing Dose (TID) effects in FPGA’s. It is shown by means of experimentation that this new design technique provides greatly improved TID tolerance for FPGAs. This study was necessary in order to make the cost of satellite manufacturing as low as possible by making use of Commercial off-the-shelf (COTS) components. However, these COTS components are very susceptible to the hazards of the space environment. One could also make use of Radiation Hard components for the purpose of satellite manufacturing, however, this will defeat the purpose of making the satellite manufacturing cost as low as possible as the cost of the radiation hard electronic components are significantly higher than their commercial counterparts. Added to this is the undesirable fact that the radiation hard components are a few generations behind as far as speed and performance is concerned, thus providing even greater motivation for making use of Commercial components. Radiation hardened components are obtained by making use of special processing methods in order to improve the components radiation tolerance. Modifying the process steps is one of the three ways to improve the radiation tolerance of an integrated circuit. The two other possibilities are to use special layout techniques or special circuit and system architectures. Another method, in which to make Complementary Metal Oxide Silicon (CMOS) circuits tolerant to ionizing radiation is to distribute the workload among redundant modules (called Switched Modular Redundancy above) in the circuit. This new method will be described in detail in this thesis.

In the immediate future, multimedia product distribution through the Internet will become main stream. However, it can also have the side effect of unauthorized duplication and distribution of multimedia products. That effect could be a critical challenge to the legal ownership of copyright and intellectual property. Many schemes have been proposed to address these issues; one is digital watermarking which is appropriate for image and video copyright protection. Videos distributed via the Internet must be processed by compression for low bit rate, due to bandwidth limitations. The most widely adapted video compression standard is MPEG-4. Discrete cosine transform (DCT) domain watermarking is a secure algorithm which could survive video compression procedures and, most importantly, attacks attempting to remove the watermark, with a visibly degraded video quality result after the watermark attacks. For a commercial broadcasting video system, real-time response is always required. For this reason, an FPGA hardware implementation is studied in this work. This thesis deals with video compression, watermarking algorithms and their hardware implementation with FPGAs. A prototyping VLSI architecture will implement video compression and watermarking algorithms with the FPGA. The prototype is evaluated with video and watermarking quality metrics. Finally, it is seen that the video qualities of the watermarking at the uncompressed vs. the compressed domain are only 1dB of PSNR lower. However, the cost of compressed domain watermarking is the complexity of drift compensation for canceling the drifting effect.

Elliptic curve cryptography (ECC) is an alternative to traditional techniques for public key cryptography. It offers smaller key size without sacrificing security level. Tate pairing is a bilinear map used in identity based cryptography schemes. In a typical elliptic curve cryptosystem, elliptic curve point multiplication is the most computationally expensive component. Similarly, Tate pairing is also quite computationally expensive. Therefore, it is more attractive to implement the ECC and Tate pairing using hardware than using software. The bases of both ECC and Tate pairing are Galois field arithmetic units. In this thesis, I propose the FPGA implementations of the elliptic curve point multiplication in GF (2283) as well as Tate pairing computation on supersingular elliptic curve in GF (2283). I have designed and synthesized the elliptic curve point multiplication and Tate pairing module using Xilinx's FPGA, as well as synthesized all the Galois arithmetic units used in the designs. Experimental results demonstrate that the FPGA implementation can speedup the elliptic curve point multiplication by 31.6 times compared to software based implementation. The results also demonstrate that the FPGA implementation can speedup the Tate pairing computation by 152 times compared to software based implementation.

Smoothing filters have been extensively used for noise removal and image restoration. Directional filters are widely used in computer vision and image processing tasks such as motion analysis, edge detection, line parameter estimation and texture analysis. It is practically impossible to tune the filters to all possible positions and orientations in real time due to huge computation requirement. The efficient way is to design a few basis filters, and express the output of a directional filter as a weighted sum of the basis filter outputs. Directional filters having these properties are called "Steerable Filters." This thesis work emphasis is on the implementation of proposed computationally efficient separable and steerable Gaussian smoothers on a Xilinx VirtexII Pro FPGA platform. FPGAs are Field Programmable Gate Arrays which consist of a collection of logic blocks including lookup tables, flip flops and some amount of Random Access Memory. All blocks are wired together using an array of interconnects. The proposed technique [2] is implemented on a FPGA hardware taking the advantage of parallelism and pipelining.