• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 234
  • 42
  • 18
  • 16
  • 4
  • 4
  • 2
  • 1
  • 1
  • 1
  • Tagged with
  • 447
  • 447
  • 442
  • 437
  • 115
  • 69
  • 64
  • 55
  • 55
  • 53
  • 51
  • 50
  • 45
  • 44
  • 39
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
331

Ethernet controller design for an embedded system using FPGA technology

Groom, Eddie L. January 2008 (has links) (PDF)
Thesis (M.S.)--University of Alabama at Birmingham, 2008. / Description based on contents viewed Oct. 7, 2008; title from PDF t.p. Includes bibliographical references (p. 80-81).
332

Built-In self-test of global routing resources in Virtex-4 FPGAs

Yao, Jia, Stroud, Charles E. January 2009 (has links)
Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographic resources (p.88-89).
333

Submicron CMOS programmable analog floating-gate circuits and arrays using DC-DC converters

Hooper, Mark S. January 2005 (has links) (PDF)
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. / Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.
334

Compiling a synchronous programming language into field programmable gate arrays /

Shen, Ying, January 1999 (has links)
Thesis (M.Eng.)--Memorial University of Newfoundland, 1999. / Bibliography: leaves 100-102.
335

Uma arquiteturaparalela baseada na codificação de huffman para otimizaçãode memória em hardware especializado para detecção de intrusão em redes

Freire, Eder Santana 13 March 2014 (has links)
Submitted by Marcio Filho (marcio.kleber@ufba.br) on 2017-06-02T13:48:59Z No. of bitstreams: 1 Dissertação - Eder Santana Freire - Revisão Final.pdf: 2884218 bytes, checksum: 8fe133e4eb9b646336edaa01f6baba6a (MD5) / Approved for entry into archive by Vanessa Reis (vanessa.jamile@ufba.br) on 2017-06-08T11:16:24Z (GMT) No. of bitstreams: 1 Dissertação - Eder Santana Freire - Revisão Final.pdf: 2884218 bytes, checksum: 8fe133e4eb9b646336edaa01f6baba6a (MD5) / Made available in DSpace on 2017-06-08T11:16:24Z (GMT). No. of bitstreams: 1 Dissertação - Eder Santana Freire - Revisão Final.pdf: 2884218 bytes, checksum: 8fe133e4eb9b646336edaa01f6baba6a (MD5) / O projeto de hardware especializado para detecção de intrusão em redes de computadores tem sido objeto de intensa pesquisa ao longo da última década, devido ao seu desempenho consideravelmente maior, comparado às implementações em software. Nesse contexto, um dos fatores limitantes é a quantidade finita de recursos de memória embarcada, em contraste com o crescente número de padrões de ameaças a serem analisados. Este trabalho propõe uma arquitetura baseada no algoritmo de Huffman para codificação, armazenamento e decodificação paralela de tais padrões, a fim de reduzir o consumo de memória embarcada em projetos de hardware destinado à detecção de intrusão em redes. Experimentos foram realizados através de simulação e síntese em FPGA de conjuntos de regras atuais do sistema de detecção de intrusão Snort, e os resultados indicaram uma economia de até 73% dos recursos de memória embarcada do chip. Adicionalmente, a utilização de uma estrutura paralelizada apresentou ganhos de desempenho significantes durante o processo de decodificação das regras.
336

Heurísticas para a fase de roteameneto de circuitos integrados baseados em FPGAs

Carvalho, Gustavo Rezende 27 March 2010 (has links)
Made available in DSpace on 2015-05-14T12:36:54Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 2485062 bytes, checksum: ad2a2349ad56d837e75386f8c9ba1027 (MD5) Previous issue date: 2010-03-27 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / The present dissertation deals with the Routing Circuits for Field Programable Gate Arrays (FPGAs). Due to the combinatorial nature of the problem, heuristics methods are commonly used to generate good quality solutions in an acceptable computationally time. In this context, a procedure based on GRASP (Greedy Randomized Adaptive Search Procedure) with a procedure of local search based on ILS (Iterated Local Search) is proposed. The algorithm has been tested in benchmark problems found in the literature, MCNC, exploring timing-driven and channel-width criteria, being able to improve 55% of the benchmarks on timing drive criteria and improve 5,3% of the benchmarks on channel width criteria. / A presente dissertação trata do problema de roteamento de circuitos para Field Programable Gate Arrays (FPGAs). Em função da natureza combinatória do problema, métodos heurísticos são comumente utilizados para gerar soluções de boa qualidade em um tempo computacionalmente aceitável. Neste contexto, um procedimento baseado na metaheurística GRASP (Greedy Randomized Adaptive Search Procedure) com um procedimento de busca local baseado em ILS (Iterated Local Search) é proposto. O algoritmo foi testado em instâncias encontradas na literatura, benchmark MCNC, explorando os critérios de tempo crítico e números de trilhas, onde mostrou-se capaz de melhorar 55% das instancias no critério de tempo crítico e 5,3% quanto ao número de trilhas.
337

Development of a soft-core based power electronic conversion controller

Nsumbu, Cassandra Daviane January 2014 (has links)
Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2014. / The application of digital control techniques has become dominant in power electronics owing to several advantages they present, when compared to analogue solutions. Their development is based on the use of microprocessors and microcontrollers, such as Application Specific Integrated Circuit (ASIC), Digital signal processors (DSP), Field Programmable Gate Arrays (FPGA), or a combination of these devices. This thesis presents an investigation of a soft-core based FPGA control system as a solution for power electronic applications. The aim was the development and implementation of a conversion controller, which purpose is to supply control inputs in the form of digital Pulse Width Modulation (PWM) signals, to a number of power electronic applications, such as single half and full bridge DC-DC converters, three phase and multicell inverters. The PWM control technique is achieved via their power semiconductor switching devices. These PWM control signals are necessary for the high frequency conversion of an analog input voltage (AC, DC or unregulated) to an analog output voltage of another level (AC or DC). This was intended to be achieved by exploiting and combining the advantages that FPGA and embedded processors provide such as high reconfigurability and multipurpose ability. This controller’s digital outputs, namely PWM switching signals, can be directly delivered to an analog signal amplification circuit to create an adequate voltage level before being processed by the converters’ switches.
338

Sistema autônomo em FPGA para captura e processamento em tempo real de imagens da pupila

Pedroni, Ricardo Umbria 28 June 2011 (has links)
Essa dissertação propõe um algoritmo e um equipamento (hardware) para captação de imagens da pupila do olho humano e processamento das mesmas a fim de obter, de forma portátil, autônoma, segura, não invasiva e em tempo real, informações sobre a pupila. Mais especificamente, o objetivo é obter informações que permitam determinar o diâmetro da pupila, tanto de forma estática (pupila com tamanho estável, sem a incidência intencional de luz) quanto dinâmica (pupila variando devido à aplicação de luz com intensidade variável). Tal sistema pode ser utilizado no setor da saúde, por exemplo, para realização da pupilometria, exame feito na área de oftalmologia, ou para medição da velocidade de expansão da pupila, exame auxiliar no diagnóstico de uma série de doenças que afetam o sistema nervoso. / This dissertation proposes an algorithm and a corresponding hardware implementation capable of capturing images from the human eye and processing these images to obtain, in a portable, autonomous, secure, and non-invasive way, in real time, information regarding the pupil. More specifically, the objective is to obtain information that allows the equipment to determine the pupil's diameter, both in static form (i.e., with constant light intensity) and in dynamic form (pupil under varying light intensity). Such a system can be used in the health sector, for example, in exams such as pupillometry, a test done by ophthalmologists, or for measuring the pupil's expansion rate, a test used in the diagnosis of a series of diseases that affect the nervous system.
339

Sistema autônomo em FPGA para captura e processamento em tempo real de imagens da pupila

Pedroni, Ricardo Umbria 28 June 2011 (has links)
Essa dissertação propõe um algoritmo e um equipamento (hardware) para captação de imagens da pupila do olho humano e processamento das mesmas a fim de obter, de forma portátil, autônoma, segura, não invasiva e em tempo real, informações sobre a pupila. Mais especificamente, o objetivo é obter informações que permitam determinar o diâmetro da pupila, tanto de forma estática (pupila com tamanho estável, sem a incidência intencional de luz) quanto dinâmica (pupila variando devido à aplicação de luz com intensidade variável). Tal sistema pode ser utilizado no setor da saúde, por exemplo, para realização da pupilometria, exame feito na área de oftalmologia, ou para medição da velocidade de expansão da pupila, exame auxiliar no diagnóstico de uma série de doenças que afetam o sistema nervoso. / This dissertation proposes an algorithm and a corresponding hardware implementation capable of capturing images from the human eye and processing these images to obtain, in a portable, autonomous, secure, and non-invasive way, in real time, information regarding the pupil. More specifically, the objective is to obtain information that allows the equipment to determine the pupil's diameter, both in static form (i.e., with constant light intensity) and in dynamic form (pupil under varying light intensity). Such a system can be used in the health sector, for example, in exams such as pupillometry, a test done by ophthalmologists, or for measuring the pupil's expansion rate, a test used in the diagnosis of a series of diseases that affect the nervous system.
340

Design under constraints of Dependability and Energy for Wireless Sensor Network / Conception sous contraintes de sûreté de fonctionnement et de consommation d’énergie, pour les réseaux de capteurs sans fil

Hoang, Van Trinh 08 December 2014 (has links)
Le contexte incertain dans lequel évoluent les applications embarquées influencefortement ces dernières. L'objectif de disponibilité induit généralement une forteredondance matérielle et fonctionnelle. A l'inverse, le paramètre de consommation prôneun nombre et un fonctionnement à minima des ressources. Avec la réduction de latechnologie, la variabilité des procédés de fabrication induit la possibilité accrue dedéfaillances. De façon à garantir une qualité de service acceptable par l'utilisateur, et cesur la totalité de la durée de vie du circuit, il convient de mener des études associant dèsles phases amont les deux paramètres sûreté de fonctionnement et consommation. Cettethèse a pour objectif de proposer une nouvelle conception pour les réseaux de capteurssans fil, afin de réduire consommation d'énergie et d'augmenter la fiabilité du réseau. / The uncertain contexts in which recent WSN embedded applications evolve have bigimpact on these applications. Traditionally, the objective of availability generally doubleshardware and functional redundancy; it means that the overhead is doubled in term ofenergy and cost. Besides, wireless node system is powered by limited battery; hencepower consumption parameter is only set to a number of components and functionalitiesat minimum resources. However, due to the technology reduction, process variabilityconducts to increase the possibility of failures. In order to guarantee an acceptablequality of service for the users, and on the operating lifetime of the system, it should carrystudies at the upper phases involving both dependability and consumption constraints.This thesis aims to propose novel design for wireless sensor networks, in order to reduceenergy consumption and to increase network dependability.

Page generated in 0.4506 seconds