In order to debug and tune stand-alone FPGA image processing configurations, it is necessary for a developer to also create the required debug tools and to implement them on the FPGA. This process takes both time and effort that could be better spent on improving the image processing algorithms. The Gate Array Terminal Operating System (GateOS) is proposed to relieve the developer of the need to construct many of these debugging tools. In GateOS we separate the image processing algorithms from the rest of the operating system. GateOS is presented to the developer as a Handel-C library, which can be customised at compile-time, to facilitate the creation of windows and widgets. Several types of widgets are described that can manipulate the parameters of image processing algorithms and enable the end-user to dynamically rearrange the position of a window on the VDU. An end user is able to interact with GateOS with both a keyboard and a mouse.

Several papers propose the use of on-line arithmetic for signal processing applications implemented on FPGAs. Although those papers provide reasonable arguments for the use of on-line arithmetic, they give only inadequate or incomplete comparisons of the proposed on-line designs to other state of the art solutions on FPGAs. In this thesis, the design, implementation and evaluation of on-line modules and networks for DSP applications, using FPGAS as the target technology, are shown. The presented designs of the modules are highly optimized for the target hardware, which allows a significant increase in efficiency compared to standard on-line designs. The design process for the networks of on-line modules is described in detail, and a methodology to analyze the dataflow and timing is presented. A comparison of on-line signal processing solutions with other approaches. that are available as IP building blocks or components, is given. It is shown that on-line designs are better in terms of latency but that they can not compete in terms of throughput and area for basic applications like FIR filters. However, it is also shown that on-line designs are able to overtake other approaches as the applications become more sophisticated. e.g. when data dependencies exist, or when non constant multiplicands restrict the use of other approaches, such as serial distributed arithmetic. For these applications, online arithmetic shows, compared to other designs, a lower latency and a significant area reduction, while maintaining a high throughput. Several properties of algorithms for which on-line arithmetic is advantageous are identified in this thesis. With this information, it is possible to determine if an on-line solution for an application should be considered. The conclusions are based on experimental data collected using CAD tools for the Xilinx XC4000 family of chips. All the designs are synthesized for the same type of devices for comparison, avoiding rough estimates of the system performance. This generates a more reliable comparison allowing designers to decide between on-line or conventional approaches for their DSP designs. / Graduation date: 2002

Advancement in cryptography over the past few decades has enabled a spectrum of security mechanisms and protocols for many applications. Despite the algorithmic security of classic cryptography, there are limitations in application and implementation of standard security methods in ultra-low energy and resource constrained systems. In addition, implementations of standard cryptographic methods can be prone to physical attacks that involve hardware level invasive or non-invasive attacks. Physical unclonable functions (PUFs) provide a complimentary security paradigm for a number of application spaces where classic cryptography has shown to be inefficient or inadequate for the above reasons. PUFs rely on intrinsic device-dependent physical variation at the microscopic scale. Physical variation results from imperfection and random fluctuations during the manufacturing process which impact each device’s characteristics in a unique way. PUFs at the circuit level amplify and capture variation in electrical characteristics to derive and establish a unique device-dependent challenge-response mapping. Prior to this work, PUF implementations were unsuitable for low power applications and vulnerable to wide range of security attacks. This doctoral thesis presents a coherent framework to derive formal requirements to design architectures and protocols for PUFs. To the best of our knowledge, this is the first comprehensive work that introduces and integrates these pieces together. The contributions include an introduction of structural requirements and metrics to classify and evaluate PUFs, design of novel architectures to fulfill these requirements, implementation and evaluation of the proposed architectures, and integration into real-world security protocols. First, I formally define and derive a new set of fundamental requirements and properties for PUFs. This work is the first attempt to provide structural requirements and guideline for design of PUF architectures. Moreover, a suite of statistical properties of PUF responses and metrics are introduced to evaluate PUFs. Second, using the proposed requirements, new and efficient PUF architectures are designed and implemented on both analog and digital platforms. In this work, the most power efficient and smallest PUF known to date is designed and implemented on ASICs that exploits analog variation in sub-threshold leakage currents of MOS devices. On the digital platform, the first successful implementation of Arbiter-PUF on FPGA was accomplished in this work after years of unsuccessful attempts by the research community. I introduced a programmable delay tuning mechanism with pico-second resolution which serves as a key component in implementation of the Arbiter-PUF on FPGA. Full performance analysis and comparison is carried out through comprehensive device simulations as well as measurements performed on a population of FPGA devices. Finally, I present the design of low-overhead and secure protocols using PUFs for integration in lightweight identification and authentication applications. The new protocols are designed with elegant simplicity to avoid the use of heavy hash operations or any error correction. The first protocol uses a time bound on the authentication process while second uses a pattern-matching index-based method to thwart reverseengineering and machine learning attacks. Using machine learning methods during the commissioning phase, a compact representation of PUF is derived and stored in a database for authentication.

Biological systems are able to perform complex movements with high energy-efficiency and, in general, can adapt to environmental changes more elegantly than traditionally engineered mechanical systems. The Equilibrium Point Hypothesis describes animal motor control as trajectories of equilibrium joint angle and joint stiffness. Traditional approaches to robot design are unable to implement this control scheme because they lack joint actuation methods that can control mechanical stiffness, and, in general, they are unable to take advantage of energy introduced into the system by the environment. In this paper, we describe the development and implementation of an FPGA-controlled, servo-actuated robotic joint that incorporates series-elastic actuation with specially developed nonlinear springs. We show that the joint's equilibrium angle and stiffness are independently controllable and that their independence is not lost in the presence of external joint torques. This approach to joint control emulates the behavior of antagonistic muscles, and thus produces a mechanical system that demonstrates biological similarity both in its observable output and in its method of control.

Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three generations of devices were designed and tested to verify the viability of such floating gate based large-scale FPAAs. Various architectures and circuit topologies were also designed and tested to explore the trade-offs present in reconfigurable analog systems. In addition, large-scale FPAAs have been incorporated into class laboratory exercises, which provide students with a much broader range of circuit and IC design experiences than have been previously possible. By combining reconfigurable analog technologies with an equivalent large-scale digital device, such as a field-programmable gate array (FPGA), an extremely powerful and flexible mixed signal development system can be produced that will enable all of the benefits possible through cooperative analog/digital signal processing (CADSP).

The FPGA GPU architecture proposed in this thesis was motivated by underserved markets for graphics processing that desire flexibility, long-term device availability, scalability, certifiability, and high reliability. These markets of industrial, medical, and avionics applications often are forced to rely on the latest GPUs that were actually designed for gaming PCs or handheld consumer devices. The architecture for the GPU in this thesis was crafted specifically for an FPGA and therefore takes advantage of its capabilities while also avoiding its limitations. Previous work did not specifically exploit the FPGA's structures and instead used FPGA implementations merely as an integration platform prior to proceeding on to a final ASIC design. The target of an FPGA for this architecture is also important because its flexibility and programmability allow the GPU's performance to be scaled or supplemented to fit unique application requirements. This tailoring of the architecture to specific requirements minimizes power consumption and device cost while still satisfying performance, certification, and device availability requirements. To demonstrate the feasibility of the flexible FPGA GPU architectural concepts, the architecture is applied to an avionics application and analyzed to confirm satisfactory results. The architecture is further validated through the development of extensions to support more comprehensive graphics processing applications. In addition, the breadth of this research is illustrated through its applicability to general-purpose computations and more specifically, scientific visualizations.

This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second signaling rates. These interfaces are becoming more prevalent in emerging designs and are difficult to test using traditional automated test equipment (ATE) and test instrumentation which were designed for testing designs utilizing synchronous and deterministic signaling. The main motivation of this research was to develop solutions that address these challenges. The methods shown in this thesis are used to design a test architecture consisting of custom hardware components, reprogrammable digital logic for hardware integration, and a software interface for external data transport and configuration. The hardware components consist of a multi-GHz field programmable gate array (FPGA) based interface board providing processing, control, and data capabilities to the system and enhanced by one or more application modules which can be tailored for specific test functionality compatible with source-synchronous and protocol interfaces. Software controls from a host computer provide high and low level access to the internal tester data and configuration memory space. The architecture described in this thesis is demonstrated through a specific test solution for a high-speed optical packet switched network called the Data Vortex. Reprogrammable firmware and software controls allow for a high degree of adaptability and application options. The modularized implementation of the hardware elements introduces additional adaptability and future upgradability, capable of incorporating new materials and design techniques for the test platform and application modules.

This dissertation exammes two of the rlsing technologies in the world of wireless, cellular communications - CDMA and the software radio. This thesis covers many of the issues related to these two emerging field s of wireless communications, establish ing a theoretical framework for the broader issues of implementation. To this end, the thesis covers many of the basic issues of spread spectrum communications, in addition to establishing the need for, and defining the role of, the software radio. Amalgamation of these two key areas of interest is embellished in a presentation of many of the concerns of implementing a specific CDMA system on a particular type of software radio - the Alcatel Altech Telecomms Flexible Radio Platform. Of primary concern in the research methodology embraced in this thesis is the mastering of a variety of analysis and implementation tools. Once the theoretical background has been substantiated by current expositions, the thesis launches along a highly deterministic route. First, the research issues are tested in a mathematical environment for suitability to the given task. Second, an analysis of the appropriateness of the technique for the software radio environment is undertaken, culminating in the attempted deployment within the hardware environmenl. Rigorous testing of the input/output mapping characteristics of the hardware instantiations created in this manner complements the research methodology with a viability study. This procedure is repeated with many elements of the CDMA system design as they are examined, simu lated, deployed and tested. / Thesis (M.Sc.Eng.)-University of Natal, Durban, 2000.

Recent advances in power electronics have lead to the wide spread adoption of advanced power supplies and energy efficient devices. This has lead to increased levels of harmonic currents in power systems, degrading the performance of electrical machinery and interfering with telecommunication services. Active filters provide a solution to these problems by compensating for the distorted currents drawn by non-linear loads. Optimal methods for controlling these active filters have been determined by computer simulation and experimental implementation. Methods used for isolating the harmonic content of an unbalanced three phase load current were compared by computer simulations. A technique based on the Fast Fourier Transform (FFT) was developed as part of this work and shown to perform favourably. Notch Filtering, Sinusoidal Subtraction, Instantaneous Reactive Power Theory, Synchronous Reference Frame and Fast Fourier Transform methods were simulated. The methods shown to be suitable for compensation of three phase unbalanced loads were implemented in a Digital Signal Processor to evaluate true performance. These methods were Notch Filtering, Sinusoidal Subtraction, Fast Fourier Transform, and a High Pass Filter based method. A completely digital hysteresis current controller for a three phase active filter inverter has been developed and implemented with a Field Programmable Gate Array. This controller interfaces directly to a digital signal processor and is resistant to electromagnetic interference. Results from the experimental hardware verified that the active filter model used for simulation is accurate, and may be used for further development of harmonic isolation methods. A technique using notch filtering gives the best performance for steady loads, with the FFT based technique giving the most flexible operation for a range of load current characteristics. Novel use of the FFT based harmonic isolation technique allows selective cancellation of individual harmonics, with particular application to multiple shunt filters connected in parallel.

While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. Two FPAAs, built using Multiple Input Translinear Elements (MITEs), have been designed, fabricated, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, current splitters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. Supporting circuitry for interfacing with current-mode, translinear FPAAs has also been developed. This circuitry included a voltage-to-current converter, a current-to-voltage converter, and a pipelined analog-to-digital converter. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.