In this thesis, I have studied CMOS dendrites, implemented them on a reconfigurable analog platform and modeled them using MATLAB Simulink. The dendrite model was further used to build a computational model. I implemented a Hidden Markov Model (HMM) classifier to build a simple YES/NO wordspotter. I also discussed the inter-relation between neural systems, CMOS transistors and HMM networks. The physical principles behind the operation of silicon devices and biological structures are similar. Hence silicon devices can be used to emulate biological structures like dendrites. Dendrites are a branched, conductive medium which connect a neurons synapses to its soma. Dendrites were previously believed to be like wires in neural networks. However, recent research suggests that they have computational power. We can emulate dendrites using transistors in the Field Programmable Analog Array (FPAA). Our lab has built the Reconfigurable Analog Signal Processor (RASP) family of FPAAs which was used for the experiments. I analytically compared the mathematical model of dendrites to our model in silicon. The mathematical model based on the device physics of the silicon devices was then used to simulate dendrites in Simulink. An automated tool, sim2spice was then used to convert the Simulink model into a SPICE netlist, such that it can be implemented on a FPAA. This is an easier tool to use for DSP and Neuromorphic engineers who's primary areas of expertise isn't circuit design.

M. Tech. Electrical Engineering. / Discusses MIMO systems have been hailed for the benefits of enhancing the reliability of the wireless communication link and increasing of the channel capacity, however the complexity of MIMO encoding and decoding algorithms increases considerably with the number of antennas. This research aims to suggest an optimisation approach to a reduced complexity implementation of the Alamouti 4×2 STBC. This is achieved by considering the FPGA parallelisation of the conditionally optimised ML decoding algorithm. The above problem can be divided into two subproblems. 1. The ML decoding of the Double Alamouti 4×2 STBC has a high computational cost when an exhaustive search is performed on the signal constellation for M-ary QAM. 2. Though the conditionally optimised ML decoding leads to less computational complexity compared to the full generic ML detection algorithm, the practical implementation remains unattractive for wireless systems.

Translinear circuits are circuits in which the exponential relationship between the output current and input voltage of a circuit element is exploited to realize various algebraic or differential equations. This thesis is concerned with a subclass of translinear circuits, in which the basic translinear element, called a multiple-input translinear element (MITE), has an output current that is exponentially related to a weighted sum of its input voltages. MITE networks can be used for the implementation of the same class of functions as traditional translinear circuits. The implementation of algebraic or (algebraic) differential equations using MITEs can be reduced to the implementation of the product-of-power-law (POPL) relationships, in which an output is given by the product of inputs raised to different powers. Hence, the synthesis of POPL relationships, and their optimization with respect to the relevant cost functions, is very important in the theory of MITE networks. In this thesis, different constraints on the topology of POPL networks that result in desirable system behavior are explored and different methods of synthesis, subject to these constraints, are developed. The constraints are usually conditions on certain matrices of the network, which characterize the weights in the relevant MITEs. Some of these constraints are related to the uniqueness of the operating point of the network and the stability of the network. Conditions that satisfy these constraints are developed in this work. The cost functions to be minimized are the number of MITEs and the number of input gates in each MITE. A complete solution to POPL network synthesis is presented here that minimizes the number of MITEs first and then minimizes the number of input gates to each MITE. A procedure for synthesizing POPL relationships optimally when the number of gates is minimal, i.e., 2, has also been developed here for the single--output case. A MITE structure that produces the maximum number of functions with minimal reconfigurability is developed for use in MITE field--programmable analog arrays. The extension of these constraints to the synthesis of linear filters is also explored, the constraint here being that the filter network should have a unique operating point in the presence of nonidealities. Synthesis examples presented here include nonlinear functions like the arctangent and the gaussian function which find application in analog implementations of particle filters. Synthesis of dynamical systems is presented here using the examples of a Lorenz system and a sinusoidal oscillator. The procedures developed here provide a structured way to automate the synthesis of nonlinear algebraic functions and differential equations using MITEs.

The Cooperative Analog/Digital Signal Processing (CADSP) research group's approach to signal processing is to see what opportunities lie in adjusting the line between what is traditionally computed in digital and what can be done in analog. By allowing more computation to be done in analog, we can take advantage of its low power, continuous domain operation, and parallel capabilities. One setback keeping Analog Signal Processing (ASP) from achieving more wide-spread use, however, is its lack of programmability. The design cycle for a typical analog system often involves several iterations of the fabrication step, which is labor intensive, time consuming, and expensive. These costs in both time and money reduce the likelihood that engineers will consider an analog solution. With CADSP's development of a reconfigurable analog platform, a Field-Programmable Analog Array (FPAA), it has become much more practical for systems to incorporate processing in the analog domain. In this Thesis, I present an entire chain of tools that allow one to design simply at the system block level and then compile that design onto analog hardware. This tool chain uses the Simulink design environment and a custom library of blocks to create analog systems. I also present several of these ASP blocks, covering a broad range of functions from matrix computation to interfacing. In addition to these tools and blocks, the most recent FPAA architectures are discussed. These include the latest RASP general-purpose FPAAs as well as an adapted version geared toward high-speed applications.

The notion of designing circuits based on charge sensing, charge adaptation, and charge programming is explored in this research. This design concept leads to a low-power capacitive sensing interface circuit that has been designed and tested with a MEMS microphone and a capacitive micromachined ultrasonic transducer. Moreover, by using the charge programming technique, a designed floating-gate based large-scale field-programmable analog array (FPAA) containing a universal sensor interface sets the stage for reconfigurable smart sensory systems. Based on the same charge programming technique, a compact programmable analog radial-basis-function (RBF) based classifier and a resultant analog vector quantizer have been developed and tested. Measurement results have shown that the analog RBF-based classifier is at least two orders of magnitude more power-efficient than an equivalent digital processor. Furthermore, an adaptive bump circuit that can facilitate unsupervised learning in the analog domain has also been proposed. A projection neural network for a support vector machine, a powerful and more complicated binary classification algorithm, has also been proposed. This neural network is suitable for analog VLSI implementation and has been simulated and verified on the transistor level. These analog classifiers can be integrated at the interface to build smart sensory systems.

This thesis presents VERTIPH, a visual programming language for the development of image processing algorithms on FPGA hardware. The research began with an examination of the whole design cycle, with a view to identifying requirements for implementing image processing on FPGAs. Based on this analysis, a design process was developed where a selected software algorithm is matched to a hardware architecture tailor made for its implementation. The algorithm and architecture are then transformed into an FPGA suitable design. It was found that in most cases the most efficient mapping for image processing algorithms is to use a streamed processing approach. This constrains how data is presented and requires most existing algorithms to be extensively modified. Therefore, the resultant designs are heavily streamed and pipelined. A visual notation was developed to complement this design process, as both streaming and pipelining can be well represented by data flow visual languages. The notation has three views each of which represents and supports a different part of the design process. An architecture view gives an overview of the design's main blocks and their interconnections. A computational view represents lower-level details by representing each block by a set of computational expressions and low-level controls. This includes a novel visual representation of pipelining that simplifies latency analysis, multiphase design, priming, flushing and stalling, and the detection of sequencing errors. A scheduling view adds a state machine for high-level control of processing blocks. This extended state objects to allow for the priming and flushing of pipelined operations. User evaluations of an implementation of the key parts of this language (the architecture view and the computational view) found that both were generally good visualisations and aided in design (especially the type interface, pipeline and control notations). The user evaluations provided several suggestions for the improvement of the language, and in particular the evaluators would have preferred to use the diagrams as a verification tool for a textual representation rather than as the primary data capture mechanism. A cognitive dimensions analysis showed that the language scores highly for thirteen of the twenty dimensions considered, particularly those related to making details of the design clearer to the developer.

This thesis presents VERTIPH, a visual programming language for the development of image processing algorithms on FPGA hardware. The research began with an examination of the whole design cycle, with a view to identifying requirements for implementing image processing on FPGAs. Based on this analysis, a design process was developed where a selected software algorithm is matched to a hardware architecture tailor made for its implementation. The algorithm and architecture are then transformed into an FPGA suitable design. It was found that in most cases the most efficient mapping for image processing algorithms is to use a streamed processing approach. This constrains how data is presented and requires most existing algorithms to be extensively modified. Therefore, the resultant designs are heavily streamed and pipelined. A visual notation was developed to complement this design process, as both streaming and pipelining can be well represented by data flow visual languages. The notation has three views each of which represents and supports a different part of the design process. An architecture view gives an overview of the design's main blocks and their interconnections. A computational view represents lower-level details by representing each block by a set of computational expressions and low-level controls. This includes a novel visual representation of pipelining that simplifies latency analysis, multiphase design, priming, flushing and stalling, and the detection of sequencing errors. A scheduling view adds a state machine for high-level control of processing blocks. This extended state objects to allow for the priming and flushing of pipelined operations. User evaluations of an implementation of the key parts of this language (the architecture view and the computational view) found that both were generally good visualisations and aided in design (especially the type interface, pipeline and control notations). The user evaluations provided several suggestions for the improvement of the language, and in particular the evaluators would have preferred to use the diagrams as a verification tool for a textual representation rather than as the primary data capture mechanism. A cognitive dimensions analysis showed that the language scores highly for thirteen of the twenty dimensions considered, particularly those related to making details of the design clearer to the developer.

This thesis presents VERTIPH, a visual programming language for the development of image processing algorithms on FPGA hardware. The research began with an examination of the whole design cycle, with a view to identifying requirements for implementing image processing on FPGAs. Based on this analysis, a design process was developed where a selected software algorithm is matched to a hardware architecture tailor made for its implementation. The algorithm and architecture are then transformed into an FPGA suitable design. It was found that in most cases the most efficient mapping for image processing algorithms is to use a streamed processing approach. This constrains how data is presented and requires most existing algorithms to be extensively modified. Therefore, the resultant designs are heavily streamed and pipelined. A visual notation was developed to complement this design process, as both streaming and pipelining can be well represented by data flow visual languages. The notation has three views each of which represents and supports a different part of the design process. An architecture view gives an overview of the design's main blocks and their interconnections. A computational view represents lower-level details by representing each block by a set of computational expressions and low-level controls. This includes a novel visual representation of pipelining that simplifies latency analysis, multiphase design, priming, flushing and stalling, and the detection of sequencing errors. A scheduling view adds a state machine for high-level control of processing blocks. This extended state objects to allow for the priming and flushing of pipelined operations. User evaluations of an implementation of the key parts of this language (the architecture view and the computational view) found that both were generally good visualisations and aided in design (especially the type interface, pipeline and control notations). The user evaluations provided several suggestions for the improvement of the language, and in particular the evaluators would have preferred to use the diagrams as a verification tool for a textual representation rather than as the primary data capture mechanism. A cognitive dimensions analysis showed that the language scores highly for thirteen of the twenty dimensions considered, particularly those related to making details of the design clearer to the developer.

Thesis (M.S.E.C.E.)--Baylor University, 2008. / Includes bibliographical references (p. 77-79).

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2011. / This thesis describes the design and implementation of a video compression development board as a standalone embedded system. The board can capture images, encode them and stream out a video to a destination over a wireless link. This project was done to allow users to test and develop video compression encoders that are designed for UAV applications. The board was designed to use an ADSP-BF533 Blackfin DSP from Analog Devices with the purpose of encoding images, which were captured by a camera module and then streamed out a video through a WiFi module. Moreover, an FPGA that has an interface to a logic analyzer, the DSP, the camera and the WiFi module, was added to accommodate other future uses, and to allow for the debugging of the board. The board was tested by loading a H.264 BP/MP encoder from Analog Devices to the DSP, where the DSP was integrated with the camera and the WiFi module. The test was successful and the board was able to encode a 2 MegaPixel picture at about 2 frames per second with a data rate of 186 Kbps. However, as the frame rate was only 2 frames per second, the video was somewhat jerky. It was found that the encoding time is a system limitation and that it has to be improved in order to increase the frame rate. A proposed solution involves dividing the captured picture into smaller segments and encoding each segment in parallel. Thereafter, the segments can be packed and streamed out. Further performance issues about the proposed structure are presented in the thesis.