Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2016. / Electricity substation monitoring and control systems have evolved over the years from simple systems capable of achieving minimalistic functions to autonomous, self-healing smart grid schemes (Farhangi, 2010). The migration of technology to networked smart grid systems was driven by the need for standardisation of communication networks, system configuration and also the reduction of system implementation costs and engineering time. Before the introduction of a uniform communication standard, legacy (non-standardised) communication protocols, for example, the Distributed Network Protocol (DNP3) were used by Remote Terminal Units (RTUs) for information exchange (Luwaca, 2014). These communication protocols could not provide a standard naming convention or data semantics since the data/information was accessed using an address-based system. The implementation of automation systems based on legacy protocols and RTUs was expensive because of parallel copper wiring required to connect instrument transformers and circuit breakers to multiple RTUs for protection and monitoring functions (Iloh et al., 2014). Legacy systems refer to Supervisory Control and Data Acquisition (SCADA) systems implemented using RTUs and legacy communication protocols. Legacy systems tended to be vendor specific because devices from different vendors did not support the same communication protocol. These issues led to the introduction of the IEC 61850 standard. The IEC 61850 standard for “communication networks and systems in a substation” provides standardised naming convention, data semantics, standardised device configuration and also device interoperability and interchangeability in some instances. The IEC 61850 standard provides a solution to expensive parallel copper wiring and standardisation issues experienced with legacy protocols. In as much as the introduction of the IEC 61850 standard addresses problems experienced with legacy system there is still a need to provide inexpensive access to IEC 61850-compliant devices and effective knowledge transfer to facilitate implementation of automation systems based on this standard. The development of an IEC 61850-compliant device requires a specialised skillset and financial investment for research and industrialisation therefore only a few vendors manufacture these devices resulting in an increase in production and manufacturing costs. For this reason this research project develops VHDL modules for mapping IEC 61850-9-2 Sampled Value (SV) messages and IEC 61850-8-1 Generic Object Oriented Substation Event (GOOSE) messages on a Field Programmable Gate Array (FPGA) platform. Sampled values are used for transmitting current and voltage transformer (CT and VT) measurements to protection devices while GOOSE messages exchange information/commands between primary equipment (CT, VT and circuit breaker) and protection devices over an Ethernet network known as the process bus.

Este trabalho tem como finalidade realizar uma análise teórica dos processos envolvidos na decodificação de códigos de bloco lineares por meio de conjuntos de informação visando otimizar esses procedimentos para viabilizar sua implementação em hardware de forma eficiente através do uso de FPGAs (do inglês Field Programmable Gate Array). Em especial, quatro contribuições são apresentadas com essa finalidade: uma versão modificada do algorítimo de Dorsch, um conjunto de algoritmos para determinar as candidatas mais prováveis e dimensionar sua quantidade de acordo com o ganho de codificação desejado aproximando seu desempenho ao do decodificador de máxima verossimilhança, uma versão implementável em hardware do critério de parada BGW (das iniciais dos autores: Barros, Godoy e Wille) e a obtenção de critérios para o dimensionamento da quantidade de intervalos de quantização a utilizar. / The purpose of this work is to undertake a theoretical analysis of the processes involved in soft-decision decoding of linear block codes using the information set approach aiming at an efficient hardware implementation in FPGAs (Field Programmable Gate Arrays). Accordingly, four contributions to this goal are presented: a modified version of the Dorsch algorithm, a set of algorithms to determine the most reliable candidates and to gauge their quantity according desired coding gain, approaching its performance to the maximum likelihood decoder, a hardware implementable version of the BGW (from the authors initials: Barros, Godoy e Wille) stop rule and the attainment of design criteria for the number of quantization intervals to apply.

Este trabalho tem como finalidade realizar uma análise teórica dos processos envolvidos na decodificação de códigos de bloco lineares por meio de conjuntos de informação visando otimizar esses procedimentos para viabilizar sua implementação em hardware de forma eficiente através do uso de FPGAs (do inglês Field Programmable Gate Array). Em especial, quatro contribuições são apresentadas com essa finalidade: uma versão modificada do algorítimo de Dorsch, um conjunto de algoritmos para determinar as candidatas mais prováveis e dimensionar sua quantidade de acordo com o ganho de codificação desejado aproximando seu desempenho ao do decodificador de máxima verossimilhança, uma versão implementável em hardware do critério de parada BGW (das iniciais dos autores: Barros, Godoy e Wille) e a obtenção de critérios para o dimensionamento da quantidade de intervalos de quantização a utilizar. / The purpose of this work is to undertake a theoretical analysis of the processes involved in soft-decision decoding of linear block codes using the information set approach aiming at an efficient hardware implementation in FPGAs (Field Programmable Gate Arrays). Accordingly, four contributions to this goal are presented: a modified version of the Dorsch algorithm, a set of algorithms to determine the most reliable candidates and to gauge their quantity according desired coding gain, approaching its performance to the maximum likelihood decoder, a hardware implementable version of the BGW (from the authors initials: Barros, Godoy e Wille) stop rule and the attainment of design criteria for the number of quantization intervals to apply.

Field-Programmable Gate Arrays (FPGAs) são largamente utilizadas em sistemas digitais por características como flexibilidade, baixo custo e alta densidade. Estas características advém do uso de células de SRAM na memória de configuração, o que torna estes dispositivos suscetíveis a erros induzidos por radiação, tais como SEUs. TMR é o método de mitigação mais utilizado, no entanto, possui um elevado custo tanto em área como em energia, restringindo seu uso em aplicações de baixo custo e/ou baixo consumo. Como alternativa a TMR, propõe-se utilizar DMR associado a um mecanismo de reparo da memória de configuração da FPGA chamado scrubbing. O reparo de FPGAs em sistemas em tempo real apresenta desafios específicos. Além da garantia da computação correta dos dados, esta computação deve se dar completamente dentro do tempo disponível (time-slot), devendo ser finalizada antes do tempo limite (deadline). A diferença entre o tempo de computação dos dados e a deadline é chamado de slack e é o tempo disponível para reparo do sistema. Este trabalho faz uso de scrubbing deslocado dinâmico, que busca maximizar a probabilidade de reparo da memória de configuração de FPGAs dentro do slack disponível, baseado em um diagnóstico do erro. O scrubbing deslocado já foi utilizado com técnicas de diagnóstico de grão fino (NAZAR, 2015). Este trabalho propõe o uso de técnicas de diagnóstico de grão grosso para o scrubbing deslocado, evitando as penalidades de desempenho e custos em área associados a técnicas de grão fino. Circuitos do conjunto MCNC foram protegidos com as técnicas propostas e submetidos a seções de injeção de erros (NAZAR; CARRO, 2012a). Os dados obtidos foram analisados e foram calculadas as melhores posição iniciais do scrubbing para cada um dos circuitos. Calculou-se a taxa de Failure-in-Time (FIT) para comparação entre as diferentes técnicas de diagnóstico propostas. Os resultados obtidos confirmaram a hipótese inicial deste trabalho que a redução do número de bits sensíveis e uma baixa degradação do período do ciclo de relógio permitiram reduzir a taxa de FIT quando comparadas com técnicas de grão fino. Por fim, uma comparação entre as três técnicas propostas é feita, analisando o desempenho e custos em área associados a cada uma. / Field-Programmable Gate Arrays (FPGAs) are widely used in digital systems due to characteristics such as flexibility, low cost and high density. These characteristics are due to the use of SRAM memory cells in the configuration memory, which make these devices susceptible to radiation-induced errors, such as SEUs. TMR is the most used mitigation technique, but it has an elevated cost both in area as well as in energy, restricting its use in low cost/low energy applications. As an alternative to TMR, we propose the use of DMR associated with a repair mechanism of the FPGA configuration memory called scrubbing. The repair of FPGA in real-time systems present a specific set of challenges. Besides guaranteeing the correct computation of data, this computation must be completely carried out within the available time (time-slot), being finalized before a time limit (deadline). The difference between the computation time and the deadline is called the slack and is the time available to repair the system. This work uses a dynamic shifted scrubbing that aims to maximize the repair probability of the configuration memory of the FPGA within the available slack based on error diagnostic. The shifted scrubbing was already proposed with fine-grained diagnostic techniques (NAZAR, 2015). This work proposes the use of coarse-grained diagnostic technique as a way to avoid the performance penalties and area costs associated to fine-grained techniques. Circuits of the MCNC suite were protected by the proposed techniques and subject to error-injection campaigns (NAZAR; CARRO, 2012a). The obtained data was analyzed and the best scrubbing starting positions for each circuit were calculated. The Failure-in-Time (FIT) rates were calculated to compare the different proposed diagnostic techniques. The obtained results validated the initial hypothesis of this work that the reduction of the number of sensitive bits and a low degradation of the clock cycle allowed a reduced FIT rate when compared with fine-grained diagnostic techniques. Finally, a comparison is made between the proposed techniques, considering performance and area costs associated to each one.

Orientador: Guido Costa Souza de Araujo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-07T08:29:26Z (GMT). No. of bitstreams: 1 Juliato_MarcioRogerio_M.pdf: 2212870 bytes, checksum: a0f8b09f80dbc648772b9b3160c6fd8f (MD5) Previous issue date: 2006 / Resumo: O aumento na comunicação utilizando-se sistemas eletrônicos tem demandado a troca de informações cifradas, permitindo a comunicação entre dois sistemas desconhecidos através de um canal inseguro (como a Internet). Criptografia baseada em curvas elípticas (ECC) é um mecanismo de chave pública que requer apenas que as entidades, que desejam se comunicar, troquem material de chave que é autêntico e possuem a propriedade de ser computacionalmente infactível descobrir a chave privada somente com informações da chave pública. A principal operação de sistemas ECC é a multiplicação de ponto (kP) que gasta 90% de seu tempo de execução na multiplicação em corpos finitos. Assim, a velocidade de um sistema ECC é altamente dependente do desempenho das operações aritméticas em corpos finitos. Nesse trabalho, estudamos a especialização de um processador NIOS2 para aplicações criptográficas em curvas elípticas. Mais precisamente,implementamos operações em corpos finitos e a multiplicação de pontos sobre F2163 como instruções especializadas e periféricos do NIOS2, e as analisamos em termos de área e speedup. Determinamos também, quais implementações s¿ao mais apropriadas para sistemas voltados a desempenho e para ambientes restritos. Nossa melhor implementação em hardware da multiplicação de pontos é capaz de acelerar o cálculo de kP em 2900 vezes, quando comparado com a melhor implementação em software executando no NIOS2. De acordo com a literatura especializada, obtivemos a mais rápida implementação da multiplicação de pontos sobre F2163 , comprovando que bases normais Gaussianas s¿ao bastante apropriadas para implementações em hardware / Abstract: The increase in electronic communication has lead to a high demand for encrypted information exchange between unfamiliar hosts over insecure channels (such as the Internet). Elliptic curve cryptography (ECC) is a public-key mechanism that requires the communicating entities exchange key material that is authentic and has the property of being computationally infeasible to determine the private key from the knowledge of the public key. The fundamental ECC operation is the point multiplication (kP), which spends around 90% of its running time in the finite field multiplication. Therefore, the speed of an ECC scheme is highly dependent on the performance of its underlying finite field arithmetic. In this work, we studied the specialization of the NIOS2 processor for ECC applications. More precisely, we implemented the finite field operations and the point multiplication over F2163 as NIOS2 custom instructions and peripherals, and thus, we analyzed them in terms of area and speedup. We also determined which implementations are best suited for performance-driven and area-constrained environments. Our best hardware implementation of the point multiplication is capable of accelerating the kP computation in 2900 times, when compared to the best software implementation running in the NIOS2. According to the literature, we obtained the fastest point multiplier in hardware over F2163 , proving that Gaussian normal bases are quite appropriate for hardware implementations / Mestrado / Arquitetura e Sistemas de Computação / Mestre em Ciência da Computação

Reliable communication over the noisy channel has become one of the major concerns in the field of digital wireless communications. The low density parity check codes (LDPC) has gained lot of attention recently because of their excellent error-correcting capacity. It was first proposed by Robert G. Gallager in 1960. LDPC codes belong to the class of linear block codes. Near capacity performance is achievable on a large collection of data transmission and storage.In my thesis I have focused on hardware implementation of (3, 6) - regular LDPC codes. A fully parallel decoder will require too high complexity of hardware realization. Partly parallel decoder has the advantage of effective compromise between decoding throughput and high hardware complexity. The decoding of the codeword follows the belief propagation alias probability propagation algorithm in log domain. A 9216 bit, (3, 6) regular LDPC code with code rate ½ was implemented on FPGA targeting Xilinx Virtex 4 XC4VLX80 device with package FF1148. This decoder achieves a maximum throughput of 82 Mbps. The entire model was designed in VHDL in the Xilinx ISE 9.2 environment.

The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs written in 8051 assembler residing in the v8051 ROM. The design can operate at speeds up to 41 MHz and used only 16% of the FPGA fabric, thus allowing complex systems to be designed on a single chip. Further research and development can be performed on v8051 to enhance performance and functionality.

This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create computational materials that can conform to the physical and computational needs of an application. PQ-cells, like cellular automata, are assembled into arrays with nearest neighbor communication and are capable of general computation. They operate asynchronously to minimize power consumption and to allow sealing without the limitations imposed by a global clock. Cell operations are stimulated by pulses which use two wires to encode a data bit. Cells are individually reconfirgurable to perform logic, move and store information, and coordinate parallel activity. The PQ-cell design targets a 0.25 μm CMOS technology. Simulation results show that a PQ-cell, when pulsed at 1.3 GHz, consumes 16.9 pJ per operation. Examples of self-timed multi-cell structures include a 98 MHz ring oscillator and a 385 MHz pipeline.

Seit einigen Jahren werden für den Entwurf anwendungsspezifischer Schaltungen verstärkt Field-Programmable Gate-Arrays (FPGAs) als Alternative zu maskenprogrammierten ASICs eingesetzt. Der Vorteil von FPGAs liegt vor allem in der schnellen und preiswerten Schaltungsentwicklung. Für den Entwurf von Schaltungen sind derzeit jedoch Software-Werkzeuge verschiedener Hersteller erforderlich. Im Rahmen eines von der Deutschen Forschungsgemeinschaft geförderten Projektes wurde gemeinsam mit der Universität Tübingen und der Technischen Universität München ein funktionsfähiges FPGA-Entwurfssystem entwickelt. Das in diesem Bericht vorgestellte Entwurfssystem beinhaltet alle wichtigen Synthese- und Layout-Komponenten zur Realisierung von Schaltungen auf FPGAs. Es wird eine Entwurfsmethodik vorgestellt, mit der alle notwendigen Entwurfsschritte bis zur Verdrahtung durchführbar sind. Ausgangspunkt ist dabei eine Schaltungsbeschreibung in verhaltensbasiertem VHDL. Für die einzelnen Systemkomponenten werden Software-Werkzeuge verwendet, die an den beteiligten Instituten entwickelt werden. Zur Ablaufsteuerung wurde eine Benutzeroberfläche entworfen, in die bisher die Technologieabbildung sowie das Layout integriert wurden.

Zur Verdrahtung der meisten FPGA-Architekturen können die aus dem ASIC-Entwurf stammenden Werkzeuge wie z.B. Kanalverdrahter nicht eingesetzt werden. Eine vollautomatische Verdrahtung mit optimalen Signallaufzeiten kann nur dann erreicht werden, wenn bei gegebener Plazierung die Leitungführung den technologischen Gegebenheiten angepaßt wird. Diese unterscheiden sich deutlich von denen in ASICs. Im Rahmen des von der Deutschen Forschungsgemeinschaft (DFG) geförderten Gemeinschafts-Projekts „FPGA Entwurfssystem“, an dem die Universität Leipzig, die Universität Tübingen und die Technischen Universität München beteiligt sind, wurden am Lehrstuhl für Computersysteme (Prof. W.G. Spruth) des Instituts für Informatik der Universität Leipzig Verfahren zur effizienten und qualitativ hochwertigen Verdrahtung von FPGA-Bausteinen entwickelt. Es wird eine Beschreibung des Verdrahtungsproblems für FPGAs gegeben und ein Lösungsansatz mit Hilfe des Branch&Bound – Verfahrens vorgestellt. Die Ergebnisse in Form von Programmlaufzeiten, Länge des kritischen Pfades und Anzahl der betrachteten Suchknoten in Abhängigkeit von einer Vielzahl von Schaltungsvarianten sind tabellarisch dargestellt und dokumentieren eine deutliche Verkürzung der längsten Pfade gegenüber dem Plazier- und Verdrahtungswerkzeug von Xilinx. Abschließend werden Probleme und weiterführende Arbeiten diskutiert.