In this thesis a microcontroller core is developed in an FPGA. Its instruction set is compatible with the microcontroller PIC16XX series by Microchip Technology. The microcontroller employs a RISC architecture with separate busses for instructions and data. Our goal in this research is to implement and evaluate the design in the FPGA. Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. Such a growing complexity demands design approaches, which can lead to designs containing millions of logic gates, memories, high-speed interfaces, and other high-performance components. In recent years, the continuous development in the area of highly integrated circuits has lead to a change in the design methods used, making it possible to economically utilize FPGAs in many designs. A test demo board from the Digilent Inc is used to fit our testing requirements of the RISC microcontroller. The test demo board also had the capability of communicating with a personal computer (PC) so that we can load the program from PC. Based on the modern design methods the microcontroller core is developed using the Verilog hardware description language. Xilinx ISE Foundation 6.3i software is used for its synthesis and implementation. An embedded test program code using MPLAB is also developed, and then loaded into the designed microcontroller residing in the FPGA. In order to perform a functional test of the microcontroller core a special test program downloader application is designed by using Borland C++ Builder. First, the specification from the PIC16XX datasheet is transferred into an abstract behavioral description. Based on that, the next step is to develop a description of the microcontroller core with some minor modifications which can be synthesizable into a FPGA. Finally, the resulting gate level netlist is evaluated and tested using a demo board.

In this thesis, we address the problem of digital intellectual property (IP) protection for the field programmable gate array (FPGA) designs. Substantial time and effort is required to the design complex circuits; thus, it makes sense to re-use these designs. An IP developer can sell his design to the companies and collect royalty. However, he needs to protect his work from security breach and piracy. The legal means of IP protection such as patents and license agreements are a deterrent to illegal IP circulation, but they are insufficient to detect an IP protection breach. Watermarking provides a means to identify the owner of a design. Firstly, we propose a watermarking technique that modifies the routing of an FPGA design to make it a function of the signature text. This watermarking technique is a type of constraint-based watermarking technique where we add a signature-based term to the routing cost function. Secondly, we need a method to verify the existence of the watermark in the design. To address this we propose a digital signature generation technique. This technique uses the switch state (ON/OFF) of certain switches on the routing to uniquely identify a design. Our results show less than 10% speed overhead for a minimum channel width routing. Increasing the channel width by unit length, we could watermark the design with a zero speed overhead. The increase in the wire length is negative for majority of the circuits. Our watermarking technique can be integrated into the current routing algorithm since it does not require an additional step for embedding the watermark. The overall design effort for routing a watermarked design is equivalent to that of routing a non-watermarked design.

Neural simulations and general dynamical system modeling consistently push the limits of available computational horsepower. This is occurring for a number of reasons: 1) models are progressing in complexity as our biological understanding increases, 2) high-level analysis tools including parameter searches and sensitivity analyses are becoming more prevalent, and 3) computational models are increasingly utilized alongside with biological preparations in a dynamic clamp configuration. General-purpose computers, as the primary target for modeling problems, are the simplest platform to implement models due to the rich variety of available tools. However, computers, limited by their generality, perform sub-optimally relative to custom hardware solutions. The goal of this thesis is to develop a new cost-effective and easy-to-use platform delivering orders of magnitude improvement in throughput over personal computers. We suggest that FPGAs, or field programmable gate arrays, provide an outlet for dramatically enhanced performance. FPGAs are high-speed, reconfigurable devices that can implement any digital logic operation using an array of parallel computing elements. Already common in fields such as signal processing, radar, medical imaging, and consumer electronics, FPGAs have yet to gain traction in neural modeling due to their steep learning curve and lack of sufficient tools despite their high-performance capability. The overall objective of this work has been to overcome the shortfalls of FPGAs to enable adoption of FPGAs within the neural modeling community. We embarked on an incremental process to develop an FPGA-based modeling environment. We first developed a prototype multi-compartment motoneuron model using a standard digital-design methodology. FPGAs at this point were shown to exceed software simulations by 10x to 100x. Next, we developed canonical modeling methodologies for manual generation of typical neural model topologies. We then developed a series of tools and techniques for analog interfacing, digital protocol processing, and real-time model tuning. This thesis culminates with the development of Dynamo, a fully-automated model compiler for the direct conversion of a model description into an FPGA implementation.

Thesis (M.S.)--University of North Texas, Aug., 2007. / Title from title page display. Includes bibliographical references.

Thesis (M.Eng)--University of Wollongong, 2005. / Typescript. Includes bibliographical references: p. 169-170.

Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references.

Thesis (M.S.)--Rochester Institute of Technology, 2008. / Typescript. Includes bibliographical references (p. 95-97).

Dissertation (PhD)--University of Stellenbosch, 2007. / Bibliography. Also available via the Internet.

Thesis (M.S.)--Ohio University, August, 1998. / Title from PDF t.p.

Thesis (M.S.)--Rochester Institute of Technology, 2008. / Typescript. Includes bibliographical references (leaves 29-32).