Cavity ringdown spectroscopy (CRDS) makes use of light retention in an optical cavity to enhance the sensitivity to absorption or extinction of light from a sample inside the cavity. When light entering the cavity is stopped, the output is an exponential decay with a decay constant that can be used to determine the quantity of the analyte if the extinction or absorption coefficient is known. The precision of the CRDS is dependent on the rate at which the system it acquires and processes ringdowns, assuming randomly distributed errors. We have demonstrated a CRDS system with a ringdown acquisition rate of 1.5 kHz, extendable to a maximum of 3.5 kHz, using new techniques that significantly changed the way in which the ringdowns are both initiated and processed. On the initiation side, we combined a custom high-resolution laser controller with a linear optical feedback configuration and a novel optical technique for initiating a ringdown. Our optical injection "unlock" method switches the laser off-resonance, while allowing the laser to immediately return to resonance, after terminating the unlock, to allow for another ringdown (on the same cavity resonance mode). This part of the system had a demonstrated ringdown initiation rate of 3.5 kHz. To take advantage of this rate, we developed an optimized cost-effective FGPA-based data acquisition and processing system for CRDS, capable of determining decay constants at a maximum rate of 4.4 kHz, by modifying a commercial ADC-FPGA evaluation board and programming it to apply a discrete Fourier transform-based algorithm for determining decay constants. The entire system shows promise with a demonstrated ability to determine gas concentrations for H2O with a measured concentration accuracy of ±3.3%. The system achieved an absorption coefficient precision of 0.1% (95% confidence interval). It also exhibited a linear response for varying H2O concentrations, a 2.2% variation (1σ) for repeated measurements at the same H2O concentration, and a corresponding precision of 0.6% (standard error of the mean). The absorption coefficient limit of detection was determined to be 1.6 x 10-8 cm-1 (root mean square of the baseline residual). Proposed modifications to our prototype system offer the promise of more substantial gains in both precision and limit of detection. The system components developed here for faster ringdown acquisition and processing have broader applications for CRDS in atmospheric science and other fields that need fast response systems operating at high-precision.

This thesis presents a new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs. We represent the netlist as the binary tree with decision variables associated with each node of the tree. The functionality of the tree nodes is chosen based on the target FPGA architecture. The proposed tree restructuring algorithms preserve local connectivity and allow direct mapping of the trees to the cellular array, thus eliminating the traditional routing phase. Also, predictability of the signal delays is a very important advantage of the developed approach. The developed bus-assignment algorithm efficiently utilizes the medium distance routing resources (buses). The method is general and can be used for any Fine Grain CA-type FPGA. To demonstrate our techniques, ATMEL 6000 series FPGA was used as a target architecture. The area and delay comparison between our methods and commercial tools is presented using a set of MCNC benchmarks. Final layouts of the implemented designs are included. Results show that the proposed techniques outperform the available commercial tools for ATMEL 6000 FPGAs, both in area and delay optimization.

Thesis (M.S. in computer engineering)--Washington State University, December 2007. / Includes bibliographical references (p. 82-83).

This thesis presents a body of work in the field of reconfigurable and neuromorphic circuits and systems. Three main projects were undertaken. The first was using a Field-Programmable Analog Array (FPAA) to model the cable behavior of dendrites using analog circuits. The second was to design, lay out, and test part of a new FPAA, the RASP 2.9v. The final project was to use floating-gate programming to remove offsets in a neuromorphic FPAA, the RASP Neuron 1D.

Reconfigurable devices are the mainstream in today’s system on chip solutions. Reconfigurable devices have the advantages of reduced cost over their equivalent custom design, quick time to market and the ability to reconfigure the design at will and ease. One such reconfigurable device is an FPGA. In this industrial thesis, the design and implementation of a control process interface using ECP2M FPGA and PCIe communication is accomplished. This control process interface is designed and implemented for a 3-D plotter system called LSC11. In this thesis, the FPGA unit implemented drives the plotter device based on specific timing requirements charted by the customer. The FPGA unit is interfaced to a Host CPU in this thesis (through PCIe communication) for controlling the LSC11 system using a custom software. All the peripherals required for the LSC11 system such as the ADC, DAC, Quadrature decoder and the PWM unit are also implemented as part of this thesis. This thesis also implements an efficient methodology to send all the inputs of the LSC11 system to the Host CPU without the necessity for issuing any cyclic read commands on the Host CPU. The RTL design is synthesised in FPGA and the system is verified for correctness and accuracy. The LSC11 system design consumed 79% of the total FPGA resources and the maximum clock frequency achieved was 130 Mhz. This thesis has been carried out at Abaxor Engineering GmbH, Germany. It is demonstrated in this thesis how FPGA aids in quick designing and implementation of system on chip solutions with PCIe communication.

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs; in this work, we apply the technique to FPGAs. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. The LUT functionality is modified to incorporate the guards and reduce toggle rates. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering gating inputs using "non-inverting paths" and trimming inputs using "partial non-inverting paths" in the circuit's AND-Inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by as much as 32% for FPGAs with 6-LUT architectures and 25% for 4-LUT architectures, on average, and can reduce power consumption in the FPGA interconnect by 29% for 6-LUTs and 27% for 4-LUTs. A clustered architecture with four LUTs to a cluster and ten LUTs to a cluster produced the best power reduction results. We implement guarded evaluation at various stages of the FPGA CAD flow and analyze the reductions. We implement the algorithm as post technology mapping, post packing and post placement optimizations. Guarded Evaluation as a post technology mapping algorithm inserted the most number of guards and hence achieved the highest activity and interconnect reduction. However, guarding signals come with a cost of increased fanout and stress on routing resources. Packing and placement provides the algorithm with additional information of the circuit which is leveraged to insert high quality guards with minimal impact on routing. Experimental results show that post-packing and post-placement methods have comparable reductions to post-mapping with considerably lesser impact on the critical path delay and routability of the circuit.

With the introduction of the floating-gate transistor into reconfigurable architectures, great advances have been made in the field. Recently, Hall et. al. have proposed the first truly large-scale field programmable analog array (FPAA). As an outgrowth of this work, a new class of FPAAs based on translinear elements has begun to be developed. The use of translinear elements, multiple input translinear elements (MITEs) specifically, allows for extreme versatility in the functions implemented by the system while keeping the computational elements of the FPAA regular. In addition, synthesis procedures have been developed for translinear elements. This facilitates the implementation of large-scale systems on the FPAA because the circuit design can be extracted using the synthesis procedures based on equations entered by the user. Two architectures are proposed for the new FPAA. The first architecture uses fine grain reconfigurability, every gate capacitor and the drain of each MITE can be connected arbitrarily, in order to create reconfigurable MITE networks. Circuits including a squaring circuit, a square root circuit, a translinear loop, a vector magnitude circuit, and a 1st-order log-domain filter were implemented using this architecture and results are presented. In addition, examples are shown to illustrate the compilation of the circuits onto the FPAA. The second proposed architecture uses a mix of fine and medium granularity in order to simplify the implementation of larger systems. Examples are given and again the compilation of the circuits onto the FPAA is shown.

A relatively new area of analog integrated circuits is emerging which is likely to have an impact on the signal processing area --analog floating-gate circuits. Analog floating- gate circuits have the potential to deliver more sophisticated signal processing at less power in a smaller space. This is the result of a novel application of digital memory technology -- the floating-gate MOSFET, that is used as an analog memory and computational device. Critical to the success of analog floating-gate circuits is on-chip programming. After investigating integrated schemes for DC-DC converters to generate the necessary voltages on chip, this research focuses on charge pumps that are integrated into the programming structure of floating-gate circuits. The impact of this research is far reaching since programmability is an indispensable feature of analog floating-gate circuits. This research lays the foundation for meeting the requirement of on-chip programming. Charge pumps will eliminate the need for high voltages to be externally supplied or regulated for analog floating-gate circuits. To the design engineer, the utilization of floating-gate circuits will look identical to their non floating-gate counterparts in terms of the value and number of supply voltages. In addition, the integration of on-chip DC-DC converters will reduce pin count, reduce board space for the implementation of the chip and facilitate distributed on chip power supplies for mixed signal integrated circuits.

Analog circuit technology is of vital importance in today's world of electronic design. Increasing prevalence of mobile electronics necessitates the search for solutions which offer high performance given tight constraints on power and chip area. Field programmable arrays utilizing floating-gate technology are one possible solution to analog design. It offers the advantages of analog processing with the additional advantage of reconfigurability, giving the designer the ability to test new analog designs without costly and time-consuming fabrication and test cycles. In this work, a new interface for FPAA's is demonstrated called Sim2spice, with which users can design signal processing systems in Matlab Simulink and compile them to SPICE circuit netlists. These netlists can be further compiled with a tool called GRASPER to a switch list for programming on an FPAA chip. Example library elements are shown, along with some compiled systems such as filters and vector-matrix multipliers. One particularly compelling application of reconfigurable analog design is the field of neuromorphic circuits, which aims to reproduce the basic functional characteristics of biological neurons and synapses in analog integrated circuit technology. Simulink libraries have been built to allow designers to build neuromorphic systems on several FPAAs that have been developed expressly for the purpose of building neurons and connecting them in networks with synapses. Several possible dynamically learning synapses have also been explored.

Thesis (M.S.)--State University of New York at Binghamton, Department of Electrical and Computer Engineering. / Includes bibliographical references (p. 55-56).