A user-friendly fully digital TDPAC-spectrometer with six detectors and fast digitizers using Field Programmable Gate Arrays is described and performance data are given.

Productivity for digital circuit design is being outpaced currently by the rate at which<br />silicon is growing such as FPGAs. Complex designs take a large amount of engineering<br />hours to complete. Reuse of existing design can potentially decrease this cost and increase<br />design productivity. However, existing digital hardware designs are not being effectively<br />reused by the hardware community due to the inability of designers to have knowledge of<br />all the attributes of designs that can be reused. In addition, designers will have to accustom<br />themselves to designs in the hardware library. By having a back-end system that looks for<br />similar circuits, there is little to no effort for the designer to reuse the design. This thesis<br />provides an overview and comparison of different methods for characterizing and comparing<br />digital circuits in order to suggest candidate circuits that engineers can reuse. Several of<br />these methods are implemented, modified, and compared to show the feasibility of utilizing<br />this work for increasing overall productivity.<br /> / Master of Science

An IVDS (Interactive Video Data Service) uses an interactive television system to transmit data to and from subscribers' homes. IVDS allows the viewer to interact with content provided on the television using a remote control. A typical IVDS application would be ordering an advertised product or playing along with a quiz show. The Virginia Tech Center for Wireless Telecommunications (CWT), under a contract with Interactive Return Service, Inc., is developing an IVDS system in which content is provided through the television cable system in the form of audio codes. A special remote control can detected these audio codes and query the user for input. The return path for this system is a wireless channel. The remote control contains a spread spectrum transmitter that transmits packets to a Repeater unit residing within a quarter mile of the user's home. With the popularity of the World Wide Web soaring, many companies are announcing internet appliances that will bring the content of the web to the user at a fraction of the cost of a standard personal computer. CWT has been contracted to extend the core IVDS system to provide a web browsing capability, allowing the user to browse the web with only the remote control. This thesis outlines the requirements of the IVDS Web Browser System. The different hardware design concepts are documented. The final Browser System specification is presented, as well as a board-level description of the Decoder Unit that is part of this final Browser System. Finally, a detailed description, current status, and simulation results are presented for the FPGA (Field Programmable Gate Array) that serves as the controller for the Decoder Unit. / Master of Science

Many problems faced in the engineering world are computationally intensive. Filtering using FIR (Finite Impulse Response) filters is an example to that. This thesis discusses the implementation of a fast, reconfigurable, and scalable FIR (Finite Impulse Response) digital filter. Constant coefficient multipliers and a Fast FIFO implementation are also discussed in connection with the FIR filter. This filter is used in two of its structures: the direct-form and the lattice structure. The thesis describes several configurations that can be created with the different components available and reports the testing results of these configurations. / Master of Science

This thesis describes the development of a multi-sensor, multi-energy x-ray prototype for automated explosives detection. The system is based on the American Science and Engineering model 101ZZ x-ray system. The 101ZZ unit received was an early model and lacked documentation of the many specialized electronic components. X-ray image quality was poor. The system was significantly modified and almost all AS&E system electronics bypassed: the x-ray source controller and conveyor belt motor were made computer controllable; the x-ray detectors were re-positioned to provide forward scatter detection capabilities; new hardware was developed to interface to the AS&E pre-amplifier boards, to collect image data from all three x-ray detectors, and to transfer the data to a personal computer. This hardware, the Differential Pair Interface Board (DPIB), is based on a Field Programmable Gate Array (FPGA) and can be dynamically re-configured to serve as a general purpose data collection device in a variety of applications. Software was also developed for the prototype system. A Windows NT device driver was written for the DPIB and a custom bus master DMA collection device. These drivers are portable and can be used as a basis for the development of other Windows NT drivers. A graphical user interface (GUI) was also developed. The GUI automates the data collection tasks and controls all the prototype system components. It interfaces with the image processing software for explosives detection and displays the results. Suspicious areas are color coded and presented to the operator for further examination. / Master of Science

Artificial neural networks are increasing in power, with attendant increases in demand for efficient processing. Performance is limited by clock speed and degree of parallelization available through multi-core processors and GPUs. With a design tailored to a specific network, a field-programmable gate array (FPGA) can be used to minimize latency without the need for geographically distributed computing. However, the task of programming an FPGA is outside the realm of most data scientists. There are tools to program FPGAs from a high level description of a network, but there is no unified interface for programmers across these tools. In this thesis, I present the design and implementation of NeuralSynth, a prototype Python framework which aims to bridge the gap between data scientists and FPGA programming for neural networks. My method relies on creating an extensible Python framework that is used to automate programming and interaction with an FPGA. The implementation includes a digital design for the FPGA that is completed by a Python framework. Programming and interacting with the FPGA does not require leaving the Python environment. The extensible approach allows multiple implementations, resulting in a similar workflow for each implementation. For evaluation, I compare the results of my implementation with a known neural network framework. / Includes bibliography. / Thesis (M.S.)--Florida Atlantic University, 2020. / FAU Electronic Theses and Dissertations Collection

A test-bench is created that injects digital pulses that emulate ATLAS LAr Front End Board electronic signal pulses in order to test prototypes. The prototypes are for new electronics for an upgrade to the CERN Large Hadron Collider that increases the rate of proton-proton collisions by an order of magnitude. This High-Luminosity Large Hadron Collider requires a completely new Trigger and Data Acquisition system to deal with information from detectors. One such system that is currently being developed is the Liquid Argon Signal Processor (LASP) whose architecture is based on Field Programmable Gate Arrays (FPGA). Validation of individual modules of the LASP are of key importance in the development cycle. Additionally, verification of module behaviour with real ATLAS pulses will not be available until much later in the project timeline. The injector project is implemented on an Intel Stratix 10 FPGA, using a soft-core NIOS II processor for TCP/IP communication with a workstation in order to transfer Monte Carlo simulation pulses to the FPGA, where it is then stored in a 2 GB DDR3 external memory. The pulses are then retrieved into internal memory buffers and are transmitted to the LASP at 40 MHz. The user is in complete control of the data pulses injected which is a vital property that would test LASP behaviour for different cases and possible failure modes. / Graduate

In recent years there has been significant research in the field of computational neuroscience and many of these biologically inspired cognitive models are based on the theory of operation of mammalian visual cortex. One such model of neocortex developed by George & Hawkins, known as Hierarchical Temporal Memories (HTM), is considered for the research discussed here. We propose a simple hierarchical model that is derived from HTM. The aim of this work is to evaluate the hardware cost and performance against software based simulations. This work presents a detailed hardware implementation and analysis of the derived hierarchical model. We show that these networks are inherently parallel in their architecture, similar to the biological computing, and that parallelism can be exploited by massively parallel architectures implemented using reconfigurable devices such as the FPGA. Hardware implementation accelerates the learning process which is useful in many real world problems. We have implemented a complex network node that operates in real time using an FPGA. The current architecture is modular and allows us to estimate the hardware resources and computational units required to realize large scale networks in the future.

Indiana University-Purdue University Indianapolis (IUPUI) / This thesis presents a Field Programmable Gate Array (FPGA) based embedded system which is used to achieve high speed segmentation of 3D images. Segmenta- tion is performed using Expectation-Maximization with Maximization of Posterior Marginals (EM/MPM) Bayesian algorithm. In this system, the embedded processor controls a custom circuit which performs the MPM and portions of the EM algorithm. The embedded processor completes the EM algorithm and also controls image data transmission between host computer and on-board memory. The whole system has been implemented on Xilinx Virtex 6 FPGA and achieved over 100 times improvement compared to standard desktop computing hardware.

The Universal Classifier Synchronizer (UCS) is a Cognitive Radio system/sensor that can detect, classify, and extract the relevant parameters from a received signal to establish physical layer communications using the received signal's profile. The current implementation is able to identify signals including AM, FM, MPSK, QAM, MFSK, and OFDM. The system is constructed to run on a Universal Software Radio Peripheral (USRP) with the GNU Radio software toolkit and also runs on an Anritsu™ signal analyzer. In both prototypes, the UCS system runs on a host computer's General Purpose Processor (GPP) and is constructed in Matlab™. The aim is to then create a portable and standalone version of the UCS system as an intermediate step towards building a future commercial implementation. This application and particular implementation aims to run on a Lyrtech SFF SDR platform and uses its FPGA and DSP modules for implementation. This platform is one of the more advanced SDR platforms available, and the aim is to develop parts of the UCS system to run on this platform. The aim is to eventually develop the complete UCS cognitive radio system on the Lyrtech SFF SDR platform that can act as a standalone portable cognitive radio system. The modules created and implanted/implemented on the SDR hardware are the Bandwidth Estimation, and Symbol Timing & Coarse Classification modules. This is the system decision path towards classification, synchronization, and demodulation of digital phase modulated signals (QAM and MPSK signal types) and also analog signals. The Digital Receiver Module (DRM) is implemented on the FPGA and takes care of all the digital down conversions, mixing, decimation, and low pass filtering. The FPGA is connected to the DSP module via a bus subsystem where the DSP receives real-time base-band complex IQ samples for further signal processing. The main UCS algorithm runs on the platform's DSP and is compiled from executable embedded C-code. Therefore, this system can then be implemented on virtually any setup that has an RF front end, digital receiver module, and processing module that will execute floating and fixed point C-code with minor changes. / Master of Science