The essential cellular functions of the mitochondrion require the exchange of a wide variety of molecules across its two membranes, which is carried out by different membrane proteins.The Voltage-Dependent Anion Channel (VDAC) located in the mitochondrial outer membrane (MOM) is responsible for the passage of various ions and small molecules to and from the intermembrane space. It is also involved in the regulation of cellular processes through its interactions with lipids or other proteins.At the MOM level, we studied the transport, through VDAC, of small inorganic ions and of thiamine pyrophosphate (TPP), an essential cofactor. Using different simulation methods such as Brownian dynamics (BD), All-Atom (AA) molecular dynamics (MD) and Coarse-Grained (CG) MD, we investigated the effect of two factors on the regulation of VDAC ion selectivity: ionic strength and membrane lipid composition. All simulation types show that VDAC becomes less selective towards anions with increasing salt concentration. The simulations further suggest that the selectivity mechanism occurs due to the filtering of some basic residues that point into the pore lumen. Furthermore, MD simulations show that the lipid composition of the membrane modulates the distribution of ions inside VDAC. In a comparison of POPE versus POPC bilayer, this regulation occurs through the more persistent interactions of some acidic residues located on both edges of the β-barrel with POPE head groups which, in turn, alters the electrostatic potential in the lumen which consequently affects the pore selectivity. CG MD simulations show that this mechanism also occurs in a mixed POPE/POPC bilayer by an enrichment of POPE on VDAC surface.In order to simulate the transport of the TPP, force field parameters have been developed and validated. Simulations of the translocation of TPP through VDAC show analogies with the mechanism used by other previously studied metabolites, in particular with ATP. At the mitochondrial inner membrane level, the mechanism of TPP transport by the specific thiamine pyrophosphate transporter (TPPT) shows significant similarities with the mechanism proposed for other members of the mitochondrial carrier family to which TPPT belongs. They mainly are the energetics arising from the alternating formation and disruption of two salt bridge networks, one on the matrix side and the other on the cytosolic side, and the interactions, of an ionic nature, formed by TPP during its binding in TPPT central cavity. Furthermore, the energy contribution provided by the cytosolic network establishes a weaker barrier than that of the matrix network, which may support the hypothesis of a uniport activity of TPPT. / Doctorat en Sciences / info:eu-repo/semantics/nonPublished

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Genetic algorithms are modern algorithms intended to solve optimization problems. Inspiration originates in evolutionary principles in nature. Parallelization of genetic algorithms provides not only faster processing but also new and better solutions. Parallel genetic algorithms are also closer to real nature than their sequential counterparts. This paper describes the most used models of parallelization of genetic algorithms. Moreover, it provides the design and implementation in programming language Python. Finally, the implementation is verified in several test cases.

A Coarse-Grained Reconfigurable Architecture (CGRA) is a processing platform which constitutes an interconnection of coarse-grained computation units (viz. Function Units (FUs), Arithmetic Logic Units (ALUs)). These units communicate directly, viz. send-receive like primitives, as opposed to the shared memory based communication used in multi-core processors. CGRAs are a well-researched topic and the design space of a CGRA is quite large. The design space can be represented as a 7-tuple (C, N, T, P, O, M, H) where each of the terms have the following meaning: C -choice of computation unit, N -choice of interconnection network, T -Choice of number of context frame (single or multiple), P -presence of partial reconfiguration, O choice of orchestration mechanism, M -design of memory hierarchy and H host-CGRA coupling. In this thesis, we develop an architectural framework for a Macro-Dataflow based CGRA where we make the following choice for each of these parameters: C -ALU, N -Network-on-Chip (NoC), T -Multiple contexts, P -support for partial reconfiguration, O -Macro Dataflow based orchestration, M -data memory banks placed at the periphery of the reconfigurable fabric (reconfigurable fabric is the name given to the interconnection of computation units), H -loose coupling between host processor and CGRA, enabling our CGRA to execute an application independent of the host-processor’s intervention. The motivations for developing such a CGRA are: To execute applications efficiently through reduction in reconfiguration time (i.e. the time needed to transfer instructions and data to the reconfigurable fabric) and reduction in execution time through better exploitation of all forms of parallelism: Instruction Level Parallelism (ILP), Data Level Parallelism (DLP) and Thread/Task Level Parallelism (TLP). We choose a macro-dataflow based orchestration framework in combination with partial reconfiguration so as to ease exploitation of TLP and DLP. Macro-dataflow serves as a light weight synchronization mechanism. We experiment with two variants of the macro-dataflow orchestration units, namely: hardware controlled orchestration unit and the compiler controlled orchestration unit. We employ a NoC as it helps reduce the reconfiguration overhead. To permit customization of the CGRA for a particular domain through the use of domain-specific custom-Intellectual Property (IP) blocks. This aids in improving both application performance and makes it energy efficient. To develop a CGRA which is completely programmable and accepts any program written using the C89 standard. The compiler and the architecture were co-developed to ensure that every feature of the architecture could be automatically programmed through an application by a compiler. In this CGRA framework, the orchestration mechanism (O) and the host-CGRA coupling (H) are kept fixed and we permit design space exploration of the other terms in the 7-tuple design space. The mode of compilation and execution remains invariant of these changes, hence referred to as a framework. We now elucidate the compilation and execution flow for this CGRA framework. An application written in C language is compiled and is transformed into a set of temporal partitions, referred to as HyperOps in this thesis. The macro-dataflow orchestration unit selects a HyperOp for execution when all its inputs are available. The instructions and operands for a ready HyperOp are transferred to the reconfigurable fabric for execution. Each ALU (in the computation unit) is capable of waiting for the availability of the input data, prior to issuing instructions. We permit the launch and execution of a temporal partition to progress in parallel, which reduces the reconfiguration overhead. We further cut launch delays by keeping loops persistent on fabric and thus eliminating the need to launch the instructions. The CGRA framework has been implemented using Bluespec System Verilog. We evaluate the performance of two of these CGRA instances: one for cryptographic applications and another instance for linear algebra kernels. We also run other general purpose integer and floating point applications to demonstrate the generic nature of these optimizations. We explore various microarchitectural optimizations viz. pipeline optimizations (i.e. changing value of T ), different forms of macro dataflow orchestration such as hardware controlled orchestration unit and compiler-controlled orchestration unit, different execution modes including resident loops, pipeline parallelism, changes to the router etc. As a result of these optimizations we observe 2.5x improvement in performance as compared to the base version. The reconfiguration overhead was hidden through overlapping launching of instructions with execution making. The perceived reconfiguration overhead is reduced drastically to about 9-11 cycles for each HyperOp, invariant of the size of the HyperOp. This can be mainly attributed to the data dependent instruction execution and use of the NoC. The overhead of the macro-dataflow execution unit was reduced to a minimum with the compiler controlled orchestration unit. To benchmark the performance of these CGRA instances, we compare the performance of these with an Intel Core 2 Quad running at 2.66GHz. On the cryptographic CGRA instance, running at 700MHz, we observe one to two orders of improvement in performance for cryptographic applications and up to one order of magnitude performance degradation for linear algebra CGRA instance. This relatively poor performance of linear algebra kernels can be attributed to the inability in exploiting ILP across computation units interconnected by the NoC, long latency in accessing data memory placed at the periphery of the reconfigurable fabric and unavailability of pipelined floating point units (which is critical to the performance of linear algebra kernels). The superior performance of the cryptographic kernels can be attributed to higher computation to load instruction ratio, careful choice of custom IP block, ability to construct large HyperOps which allows greater portion of the communication to be performed directly (as against communication through a register file in a general purpose processor) and the use of resident loops execution mode. The power consumption of a computation unit employed on the cryptography CGRA instance, along with its router is about 76mW, as estimated by Synopsys Design Vision using the Faraday 90nm technology library for an activity factor of 0.5. The power of other instances would be dependent on specific instantiation of the domain specific units. This implies that for a reconfigurable fabric of size 5 x 6 the total power consumption is about 2.3W. The area and power ( 84mW) dissipated by the macro dataflow orchestration unit, which is common to both instances, is comparable to a single computation unit, making it an effective and low overhead technique to exploit TLP.

Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using a network and this interconnection of computation elements is referred to as a reconfigurable fabric. The size of application that can be accommodated on the reconfigurable fabric is limited by the size of instruction buffers associated with each Compute element. When an application cannot be accommodated entirely, application is partitioned such that each of these partitions can be executed on the reconfigurable fabric. These partitions are scheduled by an orchestrator. The orchestrator employs dynamic dataflow execution paradigm. Dynamic dataflow execution paradigm has inherent support for synchronization and helps in exploitation of parallelism that exists across application partitions. In this thesis, we present a compiler that targets such CGRAs. The compiler presented in this thesis is capable of accepting applications specified in C89 standard. To enable architectural design space exploration, the compiler is designed such that it can be customized for several instances of CGRAs employing dataflow execution paradigm at the orchestrator. This can be achieved by specifying the appropriate configuration parameters to the compiler. The focus of this thesis is to provide efficient support for various kinds of parallelism while ensuring correctness. The compiler is designed to support fine-grained task level parallelism that exists across iterations of loops and function calls. Additionally, compiler can also support pipeline parallelism, where a loop is split into multiple stages that execute in a pipelined manner. The prototype compiler, which targets multiple instances of a CGRA, is demonstrated in this thesis. We used this compiler to target multiple variants of CGRAs employing dataflow execution paradigm. We varied the reconfigur-able fabric, orchestration mechanism employed, size of instruction buffers. We also choose applications from two different domains viz. cryptography and linear algebra. The execution time of the CGRA (the best among all instances) is compared against an Intel Quad core processor. Cryptography applications show a performance improvement ranging from more than one order of magnitude to close to two orders of magnitude. These applications have large amounts of ILP and our compiler could successfully expose the ILP available in these applications. Further, the domain customization also played an important role in achieving good performance. We employed two custom functional units for accelerating Cryptography applications and compiler could efficiently use them. In linear algebra kernels we observe multiple iterations of the loop executing in parallel, effectively exploiting loop-level parallelism at runtime. Inspite of this we notice close to an order of magnitude performance degradation. The reason for this degradation can be attributed to the use of non-pipelined floating point units, and the delays involved in accessing memory. Pipeline parallelism was demonstrated using this compiler for FFT and QR factorization. Thus, the compiler is capable of efficiently supporting different kinds of parallelism and can support complete C89 standard. Further, the compiler can also support different instances of CGRAs employing dataflow execution paradigm.

Globally Asynchronous Locally Synchronous (GALS) Field-Programmable Gate Array (FPGA) are composed of standard synchronous reconfigurable logic islands that communicate with each other via an asynchronous means. Past research into fully asynchronous FPGA has demonstrated high throughput and reliability adopting dual-rail encoding. GALS FPGAs have been proposed, relying on bundled-data encoding and fixed asynchronous communication between synchronous islands. This thesis proposes a new GALS FPGA architecture with fully reconfigurable asynchronous fabric, that relies on coarse-grained Configurable Logic Blocks (CLBs) to improve the communication capability of the device. Through datapath dedicated elements, asynchronous pipelines are efficiently mapped onto the device. The architecture is presented as well as the customized tool flow needed to compile Verilog for this new coarse-grained reconfigurable circuit.The main purpose of this thesis is to map communication-purpose user-circuits on the proposed asynchronous fabric and evaluate their performance. The benchmark circuits target the design of a Networkon-Chip (NoC) router and employ two-phase bundled-data protocol. The results are obtained through simulation and compared with the performances of the same circuits on a fine-grained classical FPGA style. The proposed architecture achieves up to 3.2x higher throughput and 2.9x lower latency than the classical one. The results show that the coarse-grained style efficiently maps asynchronous communication circuits, and it may be the starting point for future reconfigurable GALS systems. Future work should focus on improving the back-end synthesis and evaluating the FPGA GALS system as a whole. / Globala Asynkrona Lokalt Synkrona (GALS) FPGAer består av standardiserade synkrona rekonfigurerbara logiska öar som kommunicerar med varandra på ett asynkront sätt. Tidigare forskning om helt asynkrona FPGAer har demonstrerat att hög genomströmning och tillförlitlighet kan erhållas mha sk dual-rail kodning. GALS FPGA har också föreslagits, där man istället förlitar sig på kodad data och fast asynkron kommunikation mellan synkrona öar. Denna avhandling föreslår en ny GALS FPGA-arkitektur med en omkonfigurerbar asynkron struktur, bestående av sk Coarse-grained CLBs för att förbättra kommunikationsförmågan på enheten. Genom att datavägarna använder sig av dedikerade element, kan asynkrona pipelines mappas effektivt på enheten. Arkitekturen presenteras liksom det verktygsflöde som behövs för att kompilera Verilog för denna nya grovkornigt omkonfigurerbara krets.Huvudsyftet med denna avhandling är att mappa kommunikationskretsar på den föreslagna asynkrona strukturen och utvärdera dess prestanda. Referenskretsarna som används för utvärdering är en NoC router som använder sig av ett tvåfas kommunikationsprotokoll. Resultaten erhålls genom simulering och jämförs med prestanda av samma krets implementerad i en finkornig klassisk FPGA-stil. Den föreslagna arkitekturen uppnår ca 3.2x högre genomströmning och 2.9x lägre latens än den klassiska. Resultaten visar att en grovkornig stil kan mappa asynkrona kommunikationskretsar på ett effektivt sätt, och att det kan vara en bra utgångspunkt för framtida omkonfigurerbara GALS-system.Framtida arbete bör fokusera på att förbättra back-end-syntesen och att utvärdera FPGA GALS-systemet i sin helhet.

The mass of carbon trapped in methane hydrates exceeds that in conventional fossil fuel reservoirs. While methane in coarse-grained hydrate-bearing sediments is technically recoverable, most methane hydrates are found in fine-grained marine sediments where gas recovery is inherently impeded by very low gas permeability. Using experimental methods and analyses, this thesis advances the understanding of fine-grained sediments in view of gas production from methane hydrates. The research scope includes: a new approach for the classification of fines in terms of electrical sensitivity, the estimation of the sediment volume contraction during hydrate dissociation, a pore-scale study of gas migration in sediments and the self-regulation effect of surfactants, the formation of preferential gas migration pathways at interfaces during gas production, pressure core technology for the characterization of hydrate bearing sediments without causing hydrate dissociation, and the deployment of a bio-sub-sampling chamber in Japan.

This thesis considers coarse-grained models of DNA and RNA, developed in particular to study nanotechnological applications as well as some important biophysical processes. We first introduce sequence-dependent thermodynamics into a previously developed coarse-grained rigid base-pair model of DNA. This model is then used to study sequence-dependent effects in multiple DNA systems including: the heterogeneous stacking transition of single strands, the fraying of a duplex, the effects of stacking strength in the loop on the melting temperature of hairpins, the force-extension curve of single strands, and the structure of a kissing-loop complex. We further apply the DNA model to study in detail the properties of an autonomous unidirectionally propagating DNA nanotechnological device, called the ``burnt bridges motor''. We then apply the coarse-graining methods developed for the DNA model to construct a new sequence-dependent coarse-grained model of RNA, which aims to capture basic thermodynamic, structural and mechanical properties of RNA molecules. We test the model by studying its thermodynamics for a variety of secondary structure motifs and also consider the force-extension properties of an RNA duplex. This RNA model allows for efficient simulations of a variety of RNA systems up to hundreds or even thousands of base-pairs. Its versatility is further demonstrated by studying the thermodynamics of a pseudoknot folding, the formation of a kissing loop complex, the structure of a hexagonal RNA nanoring, and the unzipping of a hairpin.

A molecular dynamics coarse-grained block copolymer (BCP) model was developed and used to studied directed self-assembly (DSA), especially in regards to applications for semiconductor manufacturing. Most of the thesis is spent investigating the effect that guiding layer properties and block copolymer properties have on line roughness and defect density in a BCP-DSA process. These two effects are perhaps the most critical in making BCP-DSA a cost efficient industrial process. It is found that guiding patterns have little effect on line roughness and in fact that the BCP heals the majority of roughness in the underlying pattern. BCP properties have a larger effect on line roughness. Segregation strength (as measured by χN, where χ is the Flory- Huggins interaction parameter and N is the degree of polymerization) resulted in a larger than expected increase in line roughness when χN was low. Polydispersity resulted in a moderate increase in line roughness. In regards to equilibrium defect density, free energy calculations showed that χ was the primary determining factor, not χN as many expected. Equilibrium defect density was found to decrease exponentially with increasing χ. Defect density is also found to scale exponentially with polydispersity. Concerning defect heal rate, which can increase the real defect rate of a process if said rate is too low, it is found that increasing χN linearly increased the barrier to defect healing, which means that the defect heal rate decreases exponentially. However, for thin films this is only true for χN > ~ 50. Below χN ~ 50, the barrier is approximately constant. These results give excellent guidance to the type of materials and processes necessary to optimize a BCP-DSA process. A simulation technique designed to more efficiently sample over energy barriers called protracted noise dynamics for polymer systems was developed and studied. It was found that a decrease in simulation time of up to 4 orders of magnitude was achieved. The effect of box size on allowable pitches for a lamellar forming BCP was derived and demonstrated. It was found that more elongated boxes yielded more possible pitches and more accurate results. A short study on the effect of multiblock copolymers on the location of the order-disorder transition was also carried out and it was found that multiblock copolymers had small effect on the ODT. The distribution of chain conformations was also calculated.