De nombreuses applications imposent des contraintes de sécurité élevées (notamment au sens confidentialité et intégrité des informations manipulées). Ma thèse s'intéresse à l'accélération matérielle du système de cryptographie asymétrique basé sur les courbes elliptiques (ECC). L'environnement des systèmes visés étant rarement maîtrisé, je prends en compte l'existence potentielle d'attaquants avec un accès physique au circuit.C’est dans ce contexte qu’un crypto-processeur très flexible, compatible aussi bien avec des cibles ASIC que FPGA, a été développé. Dans le but de choisir des protections contre les attaques dites matérielles (analyse de consommation, génération de fautes, etc.), j’évalue la sécurité vis-à-vis des attaques par canaux cachés et le coût de la contre-mesure basée sur l'unification des opérations élémentaires sur des courbes elliptiques. En montant une nouvelle attaque contre un circuit mettant en œuvre des courbes quartiques de Jacobi, je montre qu’il est possible de détecter la réutilisation d’opérandes. Des expérimentations réelles m’ont permis de retrouver le secret en exploitant seulement quelques traces de puissance consommée. Je présente aussi une nouvelle protection permettant de choisir un compromis entre le niveau de sécurité, les performances et le coût. Elle est basée sur une accélération par fenêtrage aléatoire et l'utilisation optimisée d'opérations fictives. / Many applications require achieving high security level (confidentiality or integrity). My thesis is about hardware acceleration of asymmetric cryptography based on elliptic curves (ECC). These systems are rarely in a controlled environment. With this in mind, I consider potential attackers with physical access to the cryptographic device.In this context, a very flexible crypto-processor was developed that can be implemented as an ASIC or on FPGAs. To choose protections against physical attacks (power consumption analysis, fault injection, etc), I evaluate the security against side-channel attacks and the cost of the counter-measure based on operation unification. By mounting a new attack against a chip using Jacobi quartic curves, I show that re-using operands is detectable. By exploiting only some power consumption traces, I manage to recover the secret. I present also a new counter-measure allowing finding a compromise between security level, performances, and overheads. It uses random windows to accelerate computation, mixed to an optimized usage of dummy operations.

Non-invasive side-channel attacks (SCAs) are potent attacks on a cryptographic circuit that can reveal its secret key without requiring lots of equipment. EM side-channel leakage is typically the derivative of the power consumption profile of a circuit. Since the fluctuations of the supply voltage strongly depend on the topology and features of the power distribution network (PDN), design of the PDN has a direct impact on EM side-channel leakage signature. In this thesis, we explore the security implications of distributed on-chip voltage regulators against EM side-channel attacks. Extensive HFSS simulations have demonstrated that the maximum EM radiation can be reduced by 33 dB and 11 dB, respectively, at the top and bottom sides of an integrated circuit through distributed on-chip voltage regulation. The primary reason is that the power is delivered locally through partially shorter and thinner metal lines as compared to off-chip implementation.

<p>Since the discovery of graphene, two-dimensional (2D) materials have attracted broad interests for transistor applications due to their atomically thin nature. This thesis studies nano-transistors based on 2D materials for several novel applications, including tunneling transistors for low-power electronics and reconfigurable transistors for hardware security.</p><p>The first part of the thesis focuses on tunneling field-effect transistors (TFETs). Since the current injection in a conventional MOSFET depends on thermionic injection over a gate-controlled barrier, the subthreshold swing (SS) of MOSFET is fundamentally limited to 60 mV/dec at room temperature, hindering the supply voltage scaling of integrated circuits (ICs). Utilizing band-to-band tunneling (BTBT) as current injection mechanism, TFETs overcome the SS limit by filtering out the Fermi tail in the source and achieve steep-slope switching. However, existing demonstrations of TFETs are plagued by low on-currents and degraded SS, largely due to the large tunneling distances caused by non-scaled body thicknesses, making 2D materials a promising candidate as channel materials for TFETs. In this thesis, we demonstrate a prototype TFET based on black phosphorus (BP) adopting electrostatic doping that is tuned by multiple top-gates, which allows the device to be reconfigured into multiple operation modes. The band-to-band tunneling mechanism is further confirmed by source-doping-dependent and temperature-dependent measurements, and the performance improvement of BP TFETs with further body and oxide thicknesses scaling is projected by atomistic simulation. In addition, a vertical BP TFET with a large tunneling area is also demonstrated, and negative differential resistance (NDR) is observed in the device.</p><p>The second part of the thesis focuses on reconfigurable nano-transistors with tunable p- and n-type operations and the implementation of hardware security based on such transistors. Polymorphic gate has been proposed as a hardware security primitive to protect the intellectual property of ICs from reverse engineering, and its operation requires transistors that can be reconfigured between p-type and n-type. However, a traditional CMOS transistor relies on substitutional doping, and thus its polarity cannot be altered after the fabrication. By contrast, 2D nano-transistors can attain both electron and hole injections. In this thesis, we review the Schottky-barrier injection in 2D transistors and demonstrate the feasibility of achieving complementary p-type and n-type transistors using BP as channel material by adopting metal contacts with different work functions. In this design, however, the discrepancy in the p-FET and n-FET device structures makes it unsuitable for reconfigurable transistors. Therefore, we continue to modify the device design to enable reconfigurable p-type and n-type operations in the same BP transistor. Finally, a NAND/NOR polymorphic gate is experimentally demonstrated based on the reconfigurable BP transistors, showing the feasibility of using 2D materials to enable hardware security.</p><p>In the last part, we demonstrate an artificial sub-60 mV/dec switching in a metal-insulator-metal-insulator-semiconductor (MIMIS) transistor. Negative capacitance FETs (NC-FETs) have attracted wide interest as promising candidates for steep-slope devices. However, the detailed mechanisms of the observed steep-slope switching are under intense debate. We show that sub-60 mV/dec switching can be observed in a WS2 transistor with an MIMIS structure – without any ferroelectric component. Using a resistor-capacitor (RC) network model, we show that the observed steep-slope switching can be attributed to the internal gate voltage response to the chosen varying gate voltage scan rates. Our results indicate that the measurement-related artefacts can lead to observation of sub-60 mV/dec switching and that experimentalists need to critically assess their measurement setups.</p>

Replacing electronic components with molecule-sized analogs or hybrids is often seen as a promising alternative to further miniaturization of conventional electronics in the effort to achieve functional nanoscale circuit elements. In this thesis, electronic transport through self-assembled networks with tunable thiolated (alkane(di)thiol and benzenedithiol) molecule-to-colloidal gold (Au) nanoparticle ratios (1:5–50:1) is studied using a combination of broad area and scanning probe microscope-based measurements. The electronic transport paths through the network can be altered by adjusting the (di)thiol molecule–gold nanoparticle ratio and/or type of molecules in the network. Resistance can be controllably tuned by several orders of magnitude (~105 to 1011 ohms for the Au-thiolated structures studied). Two-terminal current–voltage (I-V) measurements of the Au-thiolated networks display linear behavior at low bias. High bias measurements in case of benzenedithiol networks show nonlinear negative differential resistance (NDR) and hysteresis behavior for different benzenedithiol concentrations, which can be attributed to a combination of field-assisted tunneling and charge trapping occurring in the nanoscale networks. Circuit simulations that account for different network morphologies, tunable via molecule-to-nanoparticle ratio, and defects show good agreement with the experiment and provide a guide to engineer network properties using different molecules. In addition, electronic transport properties of nanoscale networks, which are composed of Au metal clusters interconnected with thiolated molecules (benzene/alkanedithiol) and connected in linear chains and branched extended networks, are examined via first-principles density functional theory-based simulations. Calculated I-V characteristics of the metal-molecular networks exhibited nonlinearities and rectification with NDR peaks that became more pronounced with increasing chain length. The transmission spectra of the linear chains and branched networks showed an increase in the number and width of transmission peaks near the Fermi energy, as the structures were extended, indicating enhanced transmission. Peak-to-valley current NDR ratios as large as ~ 500 and rectification ratios of ~ 10 (0.25 V) were shown for linear and branched circuit elements, respectively, illustrating how charge transport through molecular-scale devices could be controlled with precision by modifying the structure and geometry of molecule-nanoparticle networks. These experimental and simulation results are utilized to propose molecular-scale circuits in applications such as memory, switching, and hardware security. The metal nanoparticle molecular electronic networks presented in this thesis provide an avenue for engineering electronics at the molecular level. / Graduate

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<p dir="ltr">The world is increasingly dependent on cyber-physical systems (CPSs), e.g., robotic vehicles (RVs) and industrial control systems (ICSs). CPSs operate autonomously by processing data coming from both “cyberspace”—such as user commands—and “physical space”—such as sensors that measure the physical environment in which they operate. However, even after decades of research, CPSs remain susceptible to threats from attackers, primarily due to the increased complexity created by interaction with cyber and physical space (e.g., the cascading effects that changes in one space can impact on the other). In particular, the complexity causes two primary threats that increase the risk of causing physical damage to RVs: (1) logic bugs causing undesired physical behavior from the developers expectations; and (2) physical sensor attacks—such as GPS or acoustic noise spoofing—that disturb an RV’s sensor readings. Dealing with these threats requires addressing the interplay between cyber and physical space. In this dissertation, we systematically analyze the interplay between cyber and physical space, thereby tackling security problems created by such complexity. We present novel algorithms to detect logic bugs (PGFuzz in Chapter 2), help developers fix them (PGPatch in Chapter 3), and test the correctness of the patches attempting to address them (PatchVerif in Chapter 4). Further, we explain algorithms to discover the root causes and formulate countermeasures against physical sensor attacks that target RVs in Chapter 5.</p>

<p dir="ltr">Sensing and communication circuits and systems are crucial components in various electronic devices and technologies. These systems are designed to acquire information from the surrounding environment through sensors, process that information, and facilitate communication between different devices or systems. It plays a vital role in modern electronic devices, enabling them to collect, process, and exchange information to perform various functions in applications such as IoB (Internet of Body), healthcare, hardware security, industrial automation, and more.</p><p dir="ltr">This work focuses on innovations in sensing and communication circuits spanning two independent application areas – human body communication and hardware emanations security.</p><p dir="ltr">First, an ultra-low power ECG monitoring system is implemented to perpetually power itself using Thermoelectric Generator (TEG) to harvest body energy while securely transmitting sensed data through on-body communication, achieving closed-loop operation without external charging or batteries. Custom circuits allow demonstrated feasibility of self-sustaining wearables leveraging Human Body Communication’s advantages.</p><p dir="ltr">Second, investigations reveal vulnerabilities introduced when repairing broken cables, with unintended monopole antennas boosting electromagnetic emissions containing signal correlations. Experiments characterize long-range detection regimes post-repair across USB keyboard cables. Further circuit and structural innovations provide localized shielding at repair points as a potential mitigation. Advancements offer contributions in understanding hardware emission security risks to inform protection strategies.</p><p dir="ltr">The two separate research work demonstrate specialized circuits advancing the state-of-the-art in sensing and communication for wearable body-based systems and hardware security through greater awareness of vulnerabilities from unintended emissions.</p><p><br></p>

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