In today’s communication devices, the need for high performance inductors is increasing as they are extensively used in RF integrated circuits (RFICs). This need is even more pronounced for variable inductors as they are widely required in tunable filters, voltage controlled amplifiers (VCO) and low noise amplifiers (LNA). For RFICs, the main tuning elements are solid state varactors that are used in conjunction with invariable inductors. However, they have limited linearity, high resistive losses, and low self resonant frequencies. This emphasizes the need for developing another tuning element that can be fabricated monolithically with ICs and can offer high range of tuning. Due to the ease of CMOS integration and low cost silicon based IC fabrication, the inductors currently used are a major source of energy loss, therefore driving the overall quality factor and performance of the chip down. During the last decade there has been an increase in research in RF MicroelectroMechanical Systems (RF MEMS) to develop high quality on chip tunable RF components. MEMS capacitors were initially proposed to substitute the existing varactors, however they can not be easily integrated on top of CMOS circuits. RF MEMS variable inductors have recently attracted attention as a better alternative. The research presented here explores using porous anodic alumina (PAA) in CMOS and MEMS fabrication. Due to its low cost and low temperature processing, PAA is an excellent candidate for silicon system integration. At first, PAA is explored as an isolation layer between the inductor and the lossy silicon substrate. Simulations show that although the dielectric constant of the PAA is tunable, the stress produced by the required thicker layers is problematic. Nevertheless, the use of PAA as a MEMS material shows much more promise. Tunable RF MEMS inductors based on bimorph sandwich layer of aluminum PAA and aluminum are fabricated and tested. A tuning range of 31% is achieved for an inductance variation of 5.8 nH to 7.6 nH at 3 GHz. To further improve the Q, bimorph layers of gold and PAA are fabricated on Alumina substrates. A lower tuning range is produced; however the quality factor performance is greatly improved. A peak Q of over 30 with a demonstrated 3% tuning range is presented. Depending on the need for either high performance or tunability, two types of tunable RF MEMS inductors are presented. Although PAA shows promise as a mechanical material for MEMS, the processing parameters (mainly stress and loss tangent) need to be improved if used as an isolation layer. To our knowledge, this is the first time this material has been proposed and successfully used as a structural material for MEMS devices and CMOS processes.

A new modified-T equivalent-circuit model for the embedded inductors in LTCC is first introduced in this thesis. The model can predict the parallel, series, and ground resonant frequencies successfully. For the embedded capacitors in LTCC, a £k-equivalent circuit that can include first two resonant frequencies has been used. One example for each model has been established to illustrate the broadband features of the models. Finally, a parameter table is given to evaluate the performance of these embedded LTCC inductors and capacitors.

Thesis (M. Phil.)--University of Hong Kong, 2001.

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

This thesis presents the design of a step-up DC-DC converter with on-chip coupled inductors. Circuit theory of DC-DC converters in general is presented, after which a mathematical model of a step up converter is developed. A circuit implementation optimized from results of the mathematical model follows. For a completely integrated step-up converter, the inductor size is reduced by increasing the frequency of operation and using a circuit topology that employs coupled inductors. Spiral inductors are also studied to achieve maximum quality factor and inductance. A fast PWM control system is used to regulate the high-frequency converter. The fabrication was done in standard TSMC 0.18-$\mu$m digital CMOS process for four circuits, including one with a conventional topology and the others with a coupled inductor topology with varying inductor geometries. Measurement results from a fabricated prototype have been presented, demonstrating the functionality of the four circuits with coupled inductors on the fabricated chip and the improvement of the coupled solution over the conventional design. It is demonstrated that the circuits with coupled inductors have a significant improvement in performance based on conversion ratio and efficiency. Finally, the design process is evaluated and recommendations are made for future work. Furthermore, a new self-oscillating and robust control system is proposed that enables simpler and more efficient regulation for high-frequency converters such as one developed for this thesis.

Thesis (M.S.)--Marquette University, 2009. / Fabien Josse, Susan Schneider, Dean Jeutter, Advisors.

M.Ing. / High frequency magnetic components have financial and physical advantages compared to low frequency magnetic components. Although high frequency magnetic components have been used for quite some time, the design and analysis of these components remain complicated.This can be ascribed to the effect of eddy currents and thermal constraints due to the smaller cooling area of such components. Planar magnetic components have long been preferred due to the higher manufacturing output, better quality control and the favorable flat shape of the component. Many studies have been conducted on planar magnetic components with respect to the energy storage capacity, air gap shape and placement, low permeability materials, to replace the air gaps, the placing of the conductors in the winding window, etc. The designs that are commonly used for planar magnetic components today, are the ones that are proven to work and not necessarily the ones that are optimal. In this study a thermal model is presented to ease the design of DC inductors. A lot of emphasis is placed on heat extraction resulting from losses in the embedded conductors through the core. This is an unconventional way to extract heat from the planar structure and leads to a new approach towards design planar inductor design.

M.Ing. / Low profile power electronics components are currently in great demand. The rapid advances in semiconductor and micro-electronics technology during the last ten years have played a major role in the creation of this demand. These advances are in turn driven by the need for compact design in computing, communication, consumer electronic goods and control systems with direct consequences in power supply design and manufacture. The study covered by this thesis involves the design, manufacture and thermal analysis of a planar inductor, which is a typical planar power electronics component. First, a throughout literature survey of planar magnetics revealed that satisfactory experimental procedures for the thermal analysis of passive power electronic components under operating conditions representative of modern applications are seldomly applied. Secondly, a computer based field-solver program and analytical methods are used to design and analyse a planar inductor. The applicability of different methods for determination of low power loss in passive components is discussed next. Finally, an experimental method suitable for low power loss determination is proposed and investigated. This method can be used in the analysis of inductors or capacitors of different sizes. It has a wide spectrum of application due to the advantages of frequency independence and different possible power levels.

As a very special DC-DC converter, VRM (Voltage Regulator Module) design must follow the fast-developing trend of microprocessors. The design challenges are the high current, high di/dt, and stringent load-line requirement. When the energy is transferred from the input of a VRM, through the VRM, then through the power delivery path to the processor, it needs sufficient capacitors to relay this energy. The capacitors' number appears to be unrealistically large if we follow today's approach for the future processors. High frequency VRM with high control bandwidth can solve this problem, however, the degradation of efficiency makes the conventional buck converter and the hard-switching isolated topologies incapable of operating at higher frequency. The research goal is to develop novel means that can help a high-output- current VRM run efficiently at high frequency. A novel Complementary Controlled Bridge (CCB) self-driven concept is proposed. With the proposed self-driven scheme, the combination of the ZVS technique and the self-driven technique recycles the gate driving energy by making use of the input capacitor of the secondary- side synchronous rectifier (SR) as the snubber capacitor of the primary-side switches. Compared to the external driver, the proposed converter can save driving loss and synchronous rectifier body diode conduction loss. Additionally, compared to the existing level-shifted self-driven scheme for bridge-type symmetrical topologies, its gate signal ringing is small and suitable for high-frequency applications. Although the CCB self-driven VRM reduces the switching frequency-related losses significantly, the conduction loss is still high. Inspired by the current-doubler concept, a novel ZVS current-tripler DC-DC converter is proposed in this work. By utilizing more SR devices to share the current during the freewheeling period, the SR conduction loss is reduced. The current-tripler DC-DC converter has a delta/delta connected transformer that can be implemented with integrated magnetics. The transformer then becomes an integrated magnetic with distributed windings, which is preferred in high current applications. The current-tripler DC-DC converter in fact meets the requirements for the CCB self-driven scheme. The two concepts are then combined with an integrated gate drive transformer. The proposed CCB self-driven concept and current-tripler concept can both be applied to the 12V non-isolated VRMs. The proposed topology is basically a buck-derived soft-switching topology with duty cycle extension and SR device self-driven capabilities. Because there is no isolation requirement, the SR gate driving becomes so simple that the voltage at the complementary controlled bridge can be used to directly drive the SR gate. Both the gate driving loss and the SR body diode conduction loss are reduced. The proposed circuit achieves similar overall efficiency to a conventional 300kHz buck converter running at 1MHz. All the circuits proposed in this dissertation can use coupling inductors to improve both the steady-state efficiency and dynamic performances. The essence of the coupling inductors concept is to provide different equivalent inductances for the steady state and the transient. Moreover, when a current loop becomes necessary to achieve proper current sharing among phases, the current loop sample hold effect will make it difficult to push the bandwidth. The sample hold effect is alleviated by the coupling inductors concept. A small-signal model is proposed to study the system dynamic performance difference with different coupling inductor designs. As the verification, the coupling concept is applied to the 12V non-isolated CCB self-driven VRM and the bandwidth as high as one third of the switching frequency is achieved, which means a significant output capacitor reduction. / Ph. D.

Power Factor Correction rectifiers are widely adopted as the first stage in most grid-tied power conversion systems. Among all PFC converts for single phase system, Boost PFC is the most popular one due to simplicity of structure and high performance. Although the efficiency of Boost PFC keeps increasing with the evolution of semiconductor technology, the intrinsic feature of high output voltage may result cumbersome system structure with multiple power conversion stages and even diminished system efficiency. This disadvantage is aggravated especially in systems where resonant converters are selected as second stage. Especially for domestic induction cooker application, step-down PFC with wide range output regulation capability would be a reasonable solution, Conventional induction cooker is composed by input filter, diode-bridge rectifier, and full bridge or half bridge series resonant circuit (SRC). High frequency magnetic field is induced through the switching action to heat the pan. The power level is usually controlled through pulse frequency modulation (PFM). In such configuration, first, a bulky input differential filter is required to filter out the high frequency operating current in SRC. Second, as the output power decreases, the operating point of SRC is moved away from the optimum point, which would result large amount circulating energy. Third, when the pan is made of well conducting and non-ferromagnetic material such as aluminum, due to the heating resistance become much smaller and peak output voltage of the switching bridge equals to the peak voltage of the grid, operating the SRC at the series resonant frequency can result excessive current flowing through the switch and the heating coil. Thus for pan with smaller heating resistance, even at maximum power, the operating frequency is pushed further away from the series resonant point, which also results efficiency loss. To address these potential issues, a PFC circuit features continuous conducting input current, high power factor, step-down capability and wide range output regulation would be preferred. The Analysis and design work is present in this article for a non-isolated hard switching DCM SEPIC PFC. Due to DCM operation of SPEIC converter, wide adjustable step-down output voltage, continuous conduction of input current and elimination of reverse recovery loss can be achieved at same time. The thesis begins with circuit operation analysis for both DC-DC and PFC operation. Based on averaged switching model, small signal model and corresponding transfer functions are derived. Especially, the impact from small intermediate capacitor on steady state value are discussed. With the concept of ripple steering, theoretic analysis is applied to SEPIC converter with two coupled inductors. The results indicate if the coupling coefficient is well designed, the equivalent input inductance can be multiple times larger than the self-inductance. Because of this, while maintaining input current ripple same, the two inductors of SEPIC can be implemented with two smaller coupled inductors. Thus both the total volume of inductors and the total number of windings can be reduced, and the power density and efficiency can be improved. Based on magnetic reluctance model, a corresponding winding scheme to control the coupling coefficient between two coupled inductors is analyzed. Also the impact of coupled inductors on the small signal transfer function is discussed. For the voltage follower control scheme of DCM PFC, single loop controller and notch filter design are discussed. With properly designed notch filter or the PR controller in another word, the closed loop bandwidth can be increased; simple PI controller is sufficient to achieve high power factor; THD of the input current can be greatly reduced. Finally, to validate the analysis and design procedure, a 1 kW prototype is built. With 120 Vrms AC input, 60V to 100V output, experimental results demonstrate unity power factor, wide output voltage regulation can be achieved within a single stage, and the 1 kW efficiency is around 93%. / Master of Science