This dissertation presents the derivation, analysis and application issues of advanced topologies with coupled inductors. The proposed innovative solutions can achieve significant performance improvement compared to the state-of-the-art technology. New applications call for high-efficiency high step-up DC-DC converters. The basic topologies suffer from extreme duty ratios and severe rectifier reverse recovery. Utilizing coupled inductor is a simple solution to avoid extreme duty ratios, but the leakage inductance associated with the coupled inductor induces severe voltage stress and loss. An innovative solution is proposed featuring with efficient leakage energy recovery and alleviated rectifier reverse recovery. Impressive efficiency improvement is achieved with a simple topology structure. The coupled inductor switching cell is identified. Topology variations and evaluations are also addressed. The concept that utilizes coupled inductors to alleviate rectifier reverse recovery is then extended, and new topologies suitable for other applications are generated. The proposed concept is demonstrated to solve the severe rectifier reverse recovery that occurs in continuous current mode (CCM) boost converters. Significant profile reduction and power density improvement can be achieved in front-end CCM power factor correction (PFC) boost converters, which are the overwhelmingly choice for use in telecommunications and server applications. This dissertation also proposes topologies to realize the single-stage parallel PFC by utilizing coupled inductors. Compared to the state-of-the-art single-stage PFC converters, the proposed topologies introduce a new power flow pattern that minimizes the bulk-capacitor voltage stress and the switch current stress. / Ph. D.

The switching noise in a hard-switched point-of-load (POL) converter may result in false turn on, electromagnetic interference issues, or even device breakdown. A resonant cross-commutated buck (rccBuck) converter operates with low noise since all MOSFETs are turned on with zero voltage within a wide load range. A state-space model was developed to calculate the voltage gain, voltage stresses, and current stresses. Design guidelines for the rccBuck converter operating at continuous voltage mode or discontinuous voltage mode are provided. The design methodology of a one-turn inductor with significant ac and dc fluxes is given. Four fabricated one-turn inductors achieved 2.1% higher efficiency and 50% smaller total magnetic volume than the commercial inductors in the same rccBuck converter. The Omni-coupled inductors (OCI), composed of a twisted E-E core and PCB windings, further improve power density and efficiency. The core loss and inductances were modeled from a complex reluctance network. According to the loss-volume Pareto fronts, the total inductor loss was minimized within a smaller volume than that of discrete inductors. The expectations were validated by an OCI-based rccBuck converter switched at 2 MHz with 12 V input, 3.3 V at 20 A output, and peak efficiency of 96.2%. The small-signal model with a good accuracy up to half switching frequency was developed based on the averaged equivalent circuit. The transient performance of an rccBuck regulator is comparable to that of a second-order buck regulator with the same switching frequency, output capacitance, and closed-loop bandwidth. / Ph. D. / The switching noise in a hard-switched point-of-load (POL) converter may result in false turn on, electromagnetic interference issues, or even device breakdown. A resonant cross-commutated buck (rccBuck) converter operates with low noise since all MOSFETs are turned on with zero voltage within a wide load range. A state-space model was developed to calculate the voltage gain, voltage stresses, and current stresses. Design guidelines for the rccBuck converter operating at continuous voltage mode or discontinuous voltage mode are provided. The design methodology of a one-turn inductor with significant ac and dc fluxes is given. Four fabricated one-turn inductors achieved 2.1% higher efficiency and 50% smaller total magnetic volume than the commercial inductors in the same rccBuck converter. The Omni-coupled inductors (OCI), composed of a twisted E-E core and PCB windings, further improve power density and efficiency. The core loss and inductances were modeled from a complex reluctance network. According to the loss-volume Pareto fronts, the total inductor loss was minimized within a smaller volume than that of discrete inductors. The expectations were validated by an OCI-based rccBuck converter switched at 2 MHz with 12 V input, 3.3 V at 20 A output, and peak efficiency of 96.2%. The small-signal model with a good accuracy up to half switching frequency was developed based on the averaged equivalent circuit. The transient performance of an rccBuck regulator is comparable to that of a second-order buck regulator with the same switching frequency, output capacitance, and closed-loop bandwidth.

There are two important issues about a spacecraft power conversion system: low ripple current flowing through both battery and bus, and bi-directional power flow to and from the battery. This thesis introduces a novel low ripple current bi-directional battery charge/discharge converter using coupled-inductor. Bi-directional switch structures and proper control scheme make it possible for the power to flow through the same converter in both directions: charging and discharging the battery. Meanwhile, the coupled-inductor is designed in such a way that all the magnetizing current (ripple current) is confined within the converter, yielding "zero-current-ripple" (ZCR) on both battery side and bus side. ZCR condition analysis, topological comparison with similar approach, and circuit design guide line are given in this thesis. Circuit operation and performance, bi-directional control strategy, and small signal characteristics of the converter are also presented along with experimental verification. / Master of Science

High power multi-level converters are deemed as the mainstay power conversion technology for renewable energy systems including the battery storage system, PV farm and electrical vehicle charge station. This thesis is focused on the study of three-level DC/DC converter with multi-phase interleaved structure, with coupled and integrated magnetics to achieve high power density. The proposed interleaved phased legs offer the benefit of output current ripple reduction, while inversed coupled inductors can suppress the circulating current between phase legs. Compared with conventional non-interleaving three-level DC/DC converter with non-coupling inductors, both inductor current ripple and output current ripple are largely reduced by interleaving with inverse-coupled inductors. Because of the non-linearity of the inductor coupling, the equivalent circuit model is developed for the proposed interleaving structure. The model identifies the existence of multiple equivalent inductances during one switching cycle. A combination of them determines the inductor current ripple and dynamics of the system. By virtue of inverse coupling and means of controlling the coupling coefficients, one can minimize the current ripple and the unwanted circulating current. To further reduce the magnetic volume, the four inductors in two-phase three-level DC/DC converter are integrated into one common structure, incorporating the negative coupling effects. The integrated magnetic structure can effectively suppress the circulating current and reduce the inductor current ripple and it is easy to manufacture. This thesis provides an equivalent circuit model to facilitate the design optimization of the integrated system. A prototype of integrated coupled inductors is assembled with nano-crystalline C-C core and powder block core. It is tested with both impedance analyzer and single pulse tester, to guarantee proper mutual inductance for inductor current ripple and output current ripple target. With a two-phase three-level DC/DC converter hardware, the concept of integrated coupled inductors is verified, showing its good performance in high-voltage, high-power conversion applications. / Master of Science / With the demanding energy consumption globally, there is an increasing trend for the requirement of high efficiency power converters with high power density. The application for renewable energies including the PV farm, battery storage system and electrical vehicle become more and more important for the sustainable development of society. High-power, high-voltage DC/DC converters can fulfill the role for such renewable energy power conversion. In this paper, a multi-phase multi-level DC/DC converter solution suitable for high-power, high-voltage application is analyzed and designed. With the techniques including interleaving operation and inverse coupled inductors, the power density for the power conversion is increased while keeping a high system efficiency. The discussed power converter in this thesis demonstrated a solution for high-power, highvoltage DC/DC power conversion with high efficiency. And the concept is verified with real hardware experimental results, showing its good performance for a 200kW power conversion system.

No description available.

Neste trabalho foi feita uma ampla pesquisa sobre blocos de RF, VCOs e LNAs, que fazem parte de transceptores. Esses blocos foram projetados utilizando um indutor externo com um alto Q, com o intuito de melhorar as principais características de desempenho de cada um dos blocos. Com a finalidade de ter um ponto de comparação foram projetados os mesmos blocos implementando todos os indutores integrados (internos). Foi proposta a utilização da tecnologia flip chip para interconectar os indutores externos aos dies dos circuitos, devido às vantagens que ela apresenta. Para implementar os indutores externos propôs-se um processo de fabricação completo, incluindo especificação das etapas de processos e dos materiais utilizados para estes indutores. Adicionalmente foi projetado um conjunto de máscaras para fabricar os indutores externos e fazer a montagem e teste dos circuitos que os utilizam. Para validar o processo proposto e caracterizar os indutores externos foram projetadas diferentes estruturas de teste. O Q do indutor externo é da ordem de 6 vezes maior que do indutor integrado, para a tecnologia escolhida. Foram projetados e fabricados dois VCOs LC: FC-VCO (Flip Chip VCO com o indutor externo), OC-VCO (On Chip VCO com o indutor interno), e dois LNAs CMOS de fonte comum cascode com degeneração indutiva: FC-LNA (Flip Chip LNA com o indutor Lg externo) e OC-LNA (On Chip LNA com todos os indutores internos). O objetivo desses quatro circuitos é demonstrar que o desempenho de circuitos RF pode ser melhorado, usando indutores externos com alto Q, conectados através de flip chip. Para implementação desses circuitos utilizou-se a tecnologia de processo AMS 0,35µm CMOS, para aplicações na banda 2,4GHz ISM, considerando o padrão Bluetooth. Foram medidos apenas os blocos com os indutores internos (OC-VCO e OC-LNA). Para os blocos com os indutores externos (FC-VCO e FC-LNA) foram apresentados os resultados de simulação pós-layout. Através da comparação dos resultados de simulação entre os VCOs foi comprovado que o uso de um indutor externo com alto Q conectado via flip chip pode melhorar significativamente o ruído de fase dos VCOs, atingindo -117dBc/Hz a 1MHz de frequência de offset para o FC-VCO, em 2,45GHz, onde a FOM é 8dB maior que o OC-VCO. Outro ganho foi através da área poupada, o FC-VCO tem uma área cerca de 83% menor que a do OC-VCO. Após as medidas elétricas do OC-VCO obteve-se um desempenho do ruído de fase de -110dBc/Hz@1MHz para 2,45GHz, e -112dBc/Hz@1MHz para 2,4GHz, o qual atende as especificações de projeto. O FC-LNA, que foi implementado com o indutor de porta Lg externo ao die, conectado via flip chip, atingiu uma figura de ruído de 2,39dB, 1,1dB menor que o OC-LNA com o mesmo consumo de potência. A área ocupada pelo FC-LNA é aproximadamente 30% menor do que o OC-LNA. Através das medidas elétricas do OC-LNA verificou-se que o circuito apresenta resultados adequados de S11 (perda de retorno da entrada) e S22 (perda de retorno da saída) na banda de frequências de interesse. No entanto, o valor do ganho apresenta uma redução em relação ao esperado. A proposta do trabalho de unir a tecnologia flip chip ao uso de indutores externos, proporciona circuitos mais compactos e consecutivamente mais baratos, pela economia de área de Si. Adicionalmente, após os indutores externos serem caracterizados, os mesmos indutores podem ser reutilizados independente da tecnologia CMOS utilizada facilitando o projeto dos blocos de RF em processos mais avançados. / This work presents a research about RF blocks that are used in Transceivers, VCOs and LNAs. These blocks were designed using a high-Q RF external inductor in order to improve the main performance characteristics. The same blocks were designed implementing all inductors on-chip (internal) in order to have a point of comparison. It was proposed the use of Flip Chip technology to interconnect the external inductors to the dies of the circuits due to the advantages that this technology offers. A full manufacturing process was proposed to implement the external inductors, including the specification of process steps and materials used for these inductors. Additionally, a set of masks was designed to fabricate the external inductors, to mount and test the circuits that used these inductors. Different test structures were designed to validate the proposed process and to characterize the external inductors. Q factor of the external inductor is around 6 times larger than the inductor integrated into the chosen IC technology. Two LC VCOs and two common-source cascode CMOS LNAs with inductive degeneration were designed and fabricated: FC-VCO (Flip Chip VCO using external inductor), OC-VCO (On Chip VCO using on-chip inductor), FCLNA (Flip Chip LNA using an external Lg inductor) and OC-LNA (On Chip LNA with all inductors implemented on-chip). The purpose of these four circuits is to demonstrate that the performance of RF circuits can be improved by using high-Q external inductors, connected by flip chip. The 0.35µm CMOS AMS technology was used to implement these circuits intended for applications in the 2.4 GHz ISM band, considering the Bluetooth standard. Were measured only the blocks with internal inductors (OC-VCO and OC-LNA). For the blocks with external inductors (FCVCO and FC-LNA) were presented the results of post-layout simulation. The comparison between the VCOs simulations results demonstrates that using an external high-Q inductor connected by flip chip can significantly improve the phase noise of VCOs. FC-VCO reached a phase noise of -117dBc/Hz at 1MHz offset frequency and a FOM 8dB greater than the OC-VCO. Another important improvement was the saved area, the FC-VCO has an area approximately 83% lower than that of OC-VCO. After electrical characterizations of the OC-VCO, phase noise performances of -110dBc/Hz@1MHz for 2.45GHz and -112dBc/Hz@1MHz for 2.4GHz were obtained, that accomplish the design specifications. FC-LNA reached a noise figure of 2.39dB, 1.1dB lower than that of OC-LNA with the same power comsumption. The total area occupied by FC-LNA is around 30% lower than that OC-LNA. Measurement results of the OC-LNA showed that the circuit presents suitable S11 (input return loss) and S22 (output return loss) values in the desired frequency band. However, the gain value presents a reduction compared with the expected values. The proposal to use the flip chip technology together with external inductors, allows more compact and cheap circuits, because Silicon area can be saved. Moreover, after the external inductors being characterized, the same inductors can be reused regardless of the CMOS technology facilitating the design of RF blocks in more advanced processes.

<p>This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors.</p><p>As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC.</p><p>Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed.</p><p>Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.</p>

Design of filters used in grid-connected inverter applications involves multiple constraints. The filter requirements are driven by tight filtering tolerances of standards such as IEEE 519-1992–IEEE Recommended Practices and Requirements for Harmonic Control in Electrical Power Systems and IEEE 1547.2-2008–IEEE Application Guide for IEEE Std 1547, IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems. Higher order LCL filters are essential to achieve these regulatory standard requirements at compact size and weight. This objective of this thesis report is to evaluate design procedures for such higher order LCL filters. The initial configuration of the third order LCL filter is decided by the frequency response of the filter. The design equations are developed in per-unit basis so results can be generalized for different applications and power levels. The frequency response is decided by IEEE specifications for high frequency current ripple at the point of common coupling. The appropriate values of L and C are then designed and constructed. Power loss in individual filter components is modeled by analytical equations and an iterative process is used to arrive at the most efficient design. Different combinations of magnetic materials (ferrite, amorphous, powder) and winding types (round wire, foil) are designed and tested to determine the most efficient design. The harmonic spectrum, power loss and temperature rise in individual filter components is predicted analytically and verified by actual tests using a 3 phase 10 kW grid connected converter setup. Experimental results of filtering characteristics show a good match with analysis in the frequency range of interconnected inverter applications. The design process is stream-lined for the above specified core and winding types. The output harmonic current spectrum is sampled and it is established that the harmonics are within the IEEE recommended limits. The analytical equations predicting the power loss and temperature rise are verified by experimental results. Based on the findings, new LCL filter combinations are formulated by varying the net Lpu to achieve the highest efficiency while still meeting the recommended IEEE specifications. Thus a design procedure which can enable an engineer to design the most efficient and compact filter that can also meet the recommended guidelines of harmonic filtering for grid-connected converter applications is established.

This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors. As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC. Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed. Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.

This thesis reports on a new implementation of high quality factor (Q) copper (Cu) inductors on CMOS-grade (10-20ohm.cm) silicon (Si) substrates using a fully CMOS-compatible process. A low-temperature (less than300C) fabrication sequence is employed to reduce the loss of Si wafers at RF frequencies by trenching the Si substrate. The high aspect-ratio (30:1) trenches are subsequently bridged over or refilled with a low-loss material to close the open areas and to create a rigid low-loss island (Trenched Si Island) on which the inductors can be fabricated. The method reported here does not require air suspension of the inductors, resulting in mechanically-robust structures that are compatible with any packaging technology. The metal loss of inductors is reduced by electroplating thick (~20m) Cu layer. Fabricated inductors are characterized and modeled from S-parameter measurement. Measurement results are in good agreement with SONNET electromagnetic simulations. A one-turn 0.8nH Cu inductor fabricated on a Trenched Silicon Island (TSI) exhibits high Q of 71 at 8.75 GHz. Whereas, the identical inductor fabricated on a 20um thick silicon dioxide (SiO2) coated standard Si substrate has a maximum Q of 41 at 1.95GHz. Comparing the Q of inductors on TSI with that of other micromachined Si substrates reveals the significant effect of trenching the Si in reduction of the substrate loss. This thesis outlines the design, fabrication, characterization and modeling of spiral type Cu inductors on the TSIs.