The 5 GHz Wireless LAN (802.11a) is a popular standard for wireless indoor communications providing moderate range and speed. Combined with the emerging ultra Wideband standard (UWB) for short range and high speed communications, the two standards promise to fulfil all areas of wireless application needs. However, due to the overlapping of the two spectrums, the stronger 802.11a signals tend to interfere causing degradation to the UWB receiver. This presents one of the main technical challenges preventing the wide acceptance of UWB. The research work presented in this thesis is to propose a low cost RF receiver front-end filter topology that would resolve the narrowband (NB) interference to UWB receiver while being operable in both 802.11a mode and UWB mode. The goal of the dual mode filter design is to reduce cost and complexity by developing a fully integrated front-end filter. The filter design utilizes high Q passive devices and Q-enhancement technique to provide front-end channel-selection in NB mode and NB interference rejection in UWB mode. In the 802.11a NB mode, the filter has a tunable gain of 4 dB to 25 dB, NF of 8 dB and an IIP3 between -47 dBm and -18 dBm. The input impedance is matched at -16 dB. The frequency of operation can be tuned from 5.15 GHz to 5.35 GHz. In the UWB mode, the filter has a gain of 0 dB to 8 dB across 3.1 GHz to 9 GHz. The filter can reject the NB interference between 5.15 GHz to 5.35 GHz at up to 60 dB. The Q of the filter is tunable up to a 250 while consuming a maximum of 23.4 mW of power. The fully integrated dual mode filter occupies a die area of 1.1 mm2.

The 5 GHz Wireless LAN (802.11a) is a popular standard for wireless indoor communications providing moderate range and speed. Combined with the emerging ultra Wideband standard (UWB) for short range and high speed communications, the two standards promise to fulfil all areas of wireless application needs. However, due to the overlapping of the two spectrums, the stronger 802.11a signals tend to interfere causing degradation to the UWB receiver. This presents one of the main technical challenges preventing the wide acceptance of UWB. The research work presented in this thesis is to propose a low cost RF receiver front-end filter topology that would resolve the narrowband (NB) interference to UWB receiver while being operable in both 802.11a mode and UWB mode. The goal of the dual mode filter design is to reduce cost and complexity by developing a fully integrated front-end filter. The filter design utilizes high Q passive devices and Q-enhancement technique to provide front-end channel-selection in NB mode and NB interference rejection in UWB mode. In the 802.11a NB mode, the filter has a tunable gain of 4 dB to 25 dB, NF of 8 dB and an IIP3 between -47 dBm and -18 dBm. The input impedance is matched at -16 dB. The frequency of operation can be tuned from 5.15 GHz to 5.35 GHz. In the UWB mode, the filter has a gain of 0 dB to 8 dB across 3.1 GHz to 9 GHz. The filter can reject the NB interference between 5.15 GHz to 5.35 GHz at up to 60 dB. The Q of the filter is tunable up to a 250 while consuming a maximum of 23.4 mW of power. The fully integrated dual mode filter occupies a die area of 1.1 mm2.

In wireless transceiver circuits some of the most prevalent required off-chip components are discrete filters. These components are generally implemented with surface acoustic wave (SAW) or ceramic components. These devices are used in the receiver section for discrimination of incoming radio frequency (RF) signals as well as downconverted intermediate frequency (IF) signals. Presently, with the growing demand for multi-functional wireless consumer devices, the need for full integration of RF and logic circuits in wireless communications systems is becoming increasingly evident. If integrated RF filters with acceptable electrical characteristics could be realized, this might reduce or eliminate the currently required off-chip filters, prospectively decreasing the complexity, size, and cost of future wireless transceiver circuits and systems. The objective of the present research effort is to implement an integrated Q-enhanced LC bandpass filter in a prospective receiver front-end RF amplifier using the passive and active components available in a standard digital complementary metal-oxide semiconductor (CMOS) process. CMOS is the standard design medium for digital circuitry, and with the increased unity gain or transit frequency (fT) values that accompany steadily shrinking CMOS device sizes, the implementation of gigahertz frequency communications circuits in this medium is increasingly feasible. The circuit design specifically investigated in this work introduces a loss-compensated second-order gigahertz range bandpass filter implemented in a 0.18 쭠digital CMOS process provided by National Semiconductor. This filter incorporates a unique design technique that provides improvements in filter linearity through an independently variable bias level shifting method, while also facilitating prospective single-to-differential signal conversion. One distinctive characteristic of the investigated circuit, in comparison to other RF integrated filter work, is the implementation of a novel integrated transformer feedback method that facilitates magnetically coupled loss-restoration and subsequent filter Q-enhancement. Additionally, this loss restoration method is achieved using a single transistor, in contrast to the multi-transistor cross-coupled transconductor Q-enhancement technique commonly implemented in other previous and current integrated RF filter research.

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling.

Design of filters used in grid-connected inverter applications involves multiple constraints. The filter requirements are driven by tight filtering tolerances of standards such as IEEE 519-1992–IEEE Recommended Practices and Requirements for Harmonic Control in Electrical Power Systems and IEEE 1547.2-2008–IEEE Application Guide for IEEE Std 1547, IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems. Higher order LCL filters are essential to achieve these regulatory standard requirements at compact size and weight. This objective of this thesis report is to evaluate design procedures for such higher order LCL filters. The initial configuration of the third order LCL filter is decided by the frequency response of the filter. The design equations are developed in per-unit basis so results can be generalized for different applications and power levels. The frequency response is decided by IEEE specifications for high frequency current ripple at the point of common coupling. The appropriate values of L and C are then designed and constructed. Power loss in individual filter components is modeled by analytical equations and an iterative process is used to arrive at the most efficient design. Different combinations of magnetic materials (ferrite, amorphous, powder) and winding types (round wire, foil) are designed and tested to determine the most efficient design. The harmonic spectrum, power loss and temperature rise in individual filter components is predicted analytically and verified by actual tests using a 3 phase 10 kW grid connected converter setup. Experimental results of filtering characteristics show a good match with analysis in the frequency range of interconnected inverter applications. The design process is stream-lined for the above specified core and winding types. The output harmonic current spectrum is sampled and it is established that the harmonics are within the IEEE recommended limits. The analytical equations predicting the power loss and temperature rise are verified by experimental results. Based on the findings, new LCL filter combinations are formulated by varying the net Lpu to achieve the highest efficiency while still meeting the recommended IEEE specifications. Thus a design procedure which can enable an engineer to design the most efficient and compact filter that can also meet the recommended guidelines of harmonic filtering for grid-connected converter applications is established.

An approach with ¡§consecutive orthogonal arrays (COA)¡¨ is proposed for solving the problems in designing power electronic circuits. This approach is conceptually based on the orthogonal array method, which has been successfully implemented in quality engineering. The circuit parameters to be determined are assigned as the controlled variables of the orthogonal arrays. Incorporating with the inferential rules, the average effects of each control variable levels are used as the indices to determine the control variable levels of the subsequent orthogonal array. By manipulating on COA, circuit parameters with the desired circuit performances can be found from an effectively reduced number of numerical calculations or experimental tests. In this dissertation, the method with COA is implemented on solving four problems often encountered in the design of power electronic circuits. The first problem one has to deal with is to find a combination with the best performance from a great number of analyzed results. The illustrative example is the design of LC passive filters. Using COA method, the desired component values of the filter can be effectively and efficiently found with far fewer calculations. The second design problem arises from the non-linearity of circuit. An experienced engineer may be able to figure out circuit parameters with satisfactory performance based on their pre-knowledge on the circuit. Nevertheless, they are always questioned whether a better choice can be made. The typical case is the self-excited resonant electronic ballast with the non-linear characteristics of the saturated transformer and the power transistor storage-time. In this case, the average effects of COA obtained from experimental tests are used as the observational indexes to search a combination of circuit parameters for the desired lamp power. The third problem is that circuit functions are mutually exclusive. The designers are greatly perplexed to decide the circuit parameters, with which all functions should be met at the same time. The method with COA is applied to design a filter circuit to achieve the goals of low EMI noise and high power factor simultaneously. Finally, one has to cope with the effects of the uncontrolled variables, such as: ambient temperature, divergence among different manufacturers, and used hours. By applying COA with inferential rules, electronic ballasts can be robustly designed to operate fluorescent lamps at satisfied performance under the influence of these uncontrolled variables.

Mikronät är ett självförsörjande elnät och används bland annat då elektriskaprodukter kräver en AC-spänning men inte har tillgång till huvudnätet. Målet idetta projekt är att dimensionera och analysera de olika delarna som ett mikronätbestår av, för att sedan konstruera och testa ifall den uppfyller kraven utifrånvissa specifikationer.Metoderna som används för att dimensionera och analysera mikronätet bestårfrämst av beräkningar och simuleringar samt konstruktion av enstaka kretsar.Mikronätet består av en AC-drive, ett lågpassfilter och trefastransformator.Mikronätet konstrueras med en varierbar frekvens mellan 45 och 65 Hz, samtomvandling av 540 VDC till 400 VAC.

This thesis deals with control of three phase inverter as three phase sinusoidal voltage source for UPS application. Thesis is split to two parts, teoretical and practical. Teoretical part deals with three phase inverter topology analysis according requirement of neutral line wire and possibilities of generating sinusoidal PWM in depend of topology. There are also analysed properties of contorled system and designed 3 regulation methods with simulations. Second part of thesis deals with realisation of sinusoidal power source with inverter borrowed by Elcom company. To inverter control is used digital signal controler TMS320F28335 with implemented control algorithms. There are also presented the measurement results of the prototype of power source. In conclusion, simulation results are compared with measurements and achieved results are summarized.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-04-18T14:49:13Z No. of bitstreams: 1 igordiasnetodesouza.pdf: 13872772 bytes, checksum: 45517d7a6da7ae06ecacec6a7fb7ebd8 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-04-18T14:50:11Z (GMT) No. of bitstreams: 1 igordiasnetodesouza.pdf: 13872772 bytes, checksum: 45517d7a6da7ae06ecacec6a7fb7ebd8 (MD5) / Made available in DSpace on 2017-04-18T14:50:11Z (GMT). No. of bitstreams: 1 igordiasnetodesouza.pdf: 13872772 bytes, checksum: 45517d7a6da7ae06ecacec6a7fb7ebd8 (MD5) Previous issue date: 2017-02-17 / Esta dissertação apresenta um estudo de um conversor emulador de rede (CER) que faz parte de uma estrutura Power-Hardware-in-the-Loop (PHIL). O PHIL será futuramente utilizado para verificar os impactos causados pela integração de sistemas de geração fotovoltaico (PV) à rede elétrica, assim como a operação do sistema PV frente a distúrbios na rede. O CER, composto por um conversor fonte de tensão (VSC) de dois níveis e filtro de saída LC, é responsável por alimentar cargas isoladas emulando uma rede elétrica. A modelagem do conversor emulador de rede é feita no sistema de coordenadas estacionário (αβ0), fornecendo um sistema de equações diferenciais usado para descrever o comportamento dinâmico do sistema. O conversor é controlado no modo de tensão, através da estratégia de modulação vetorial. Duas malhas de controle em cascata são projetadas. A malha interna utiliza compensadores em avanço digitais para amortecer a ressonância do filtro LC sem a necessidade de uma realimentação interna de corrente. Já a externa utiliza controladores ressonantes digitais modificados para rejeitar distúrbios harmônicos e garantir a qualidade da forma de onda da tensão no ponto de acoplamento comum. Os controladores ressonantes são conectados em série e o projeto é baseado no amortecimento dos zeros. Resultados experimentais, obtidos com o protótipo de laboratório, cujos controladores foram implementados em um processador digital de sinais TMS320F28335 da Texas Instruments, são usados para validar as estratégias de controle propostas. / This dissertation presents a study on a grid-former converter (GFC) which is a part of a Power-Hardware-in-the-Loop (PHIL) structure. The PHIL will be used to verify the impacts caused by the integration of photovoltaic (PV) generation systems into grid, as well as to study the PV operation under grid disturbances. The GFC, composed by a two-level voltage source converter with a LC output filter, is responsible to feed isolated loads emulating an electrical grid. The modeling of the grid-former converter is done in the stationary frame (αβ0), providing a set of differential equations that describes the dynamical behavior of the system. The converter is controlled in voltage mode by means of the space vector modulation (SVM) strategy. Two control loops are designed to control the static converter. At the inner loop a novel discrete-time active damping technique is proposed in order to damp the filter resonance without the need of current feedback. The method is based on an inner feedback loop with digital lead compensator on the feedback path while the external loop uses a discretetime integrator and a modified digital resonant controller to guarantee a decreasing frequency response and ensure the quality of the voltage waveform at the point of common coupling, respectively. The resonant controllers are connected in series and the design is based on its zeros damping. Experimental results obtained with the prototype, which controllers were implemented in a Texas Instruments TMS320F28335 are used to validate the proposed control strategies.

This master‘s thesis focuses on optimization of power and control circuits of an inverter, which was developed at UVEE. The principle of function and circuit implementation of a single-phase inventer, various calculations (design of an LC filter, DC link capacitor, semiconductor elements and heat sink) are described in the thesis. A design of fast overcurrent protections, oscillator and saw signal generator is included. Furthermore, a printed circuit board was designed which was optimized by thermal simulation in the Workbench Ansys. Subsequently, the printed circuit board was mounted, debugged and verification measurements were performed on it. At the end of the thesis there is a documentation for the implemented equipment.