Thesis (Ph. D.)--University of Texas at Austin, 2005. / Vita. Includes bibliographical references.

In search of higher speed and integration, the integrated circuit (IC) technology is scaling down. The total on-chip interconnect length is increasing exponentially. In fact, interconnect takes up the most part of the total chip area. The parasitics associated with these interconnect have significant impact on the circuit performance. Some of the effects of parasitics include cross talk, voltage drop and high current density. These issues can result in cross-talk induced functional failure and failures due to IR drop and electro-migration. This has resulted in interconnect- driven design trend in state-of-the-art integrated circuits. Reliability analysis, that includes simulating the effects of parasitics for voltage drop, current density, has become one of the most important steps in the VLSI design flow. Most of the CAD/EDA tools available, map these analysis results two dimensionally. Al- though this helps the designer, providing a three dimensional view of these results is highly desirable when dealing with complex circuits. In pursuit of visualizing reliability analysis results three dimensionally, as a first step, this work presents a tool that can visualize IC interconnect three di- mensionally. Throughout the course of this research open source tools were used to achieve the objective. In this work the circuit layout is stored as an OpenAc- cess database. A C++ program reads the design information using OpenAccess API and converts it to the .OBJ file format. Art of Illusion, an open source 3D modeling and rendering tool, reads this .OBJ file and models the IC interconnect three-dimensionally. In addition, Eclipse, an open source java IDE is used as a development platform. The tool presented has the capability to zoom in, zoom out and pan in real time.

There are basically three methods of designing Very Large Scale Integrated (VLSI) circuits; Gate Array, Standard Cell, and Full Custom. The objective of this research is to design a VLSI circuit using the Standard Cell approach. A prime requisite for a successful design of these circuits is an integrated Computer Aided Design (CAD) system. The chip design requirements for an integrated CAD system are developed and their interrelationships are presented. As VLSI circuits grow in complexity, the problem of how to test them becomes more difficult. Two methods for testing are defined: 1. Insertion within the system of which the chip is a part, and use of standard system test techniques. 2. Self-test circuitry built into the chip. These testing techniques were used in the VLSI circuit in this report.

In the early 1990's, with the boom of the Internet and the advancements in telecommunications, the demand for high-speed communications systems has reached every corner of the world in forms such as, phone exchanges, the internet servers, routers, and all other types of telecommunication systems. These communication systems demand more data computing, storage, and retrieval capabilities at higher speeds, these demands place a great strain on the power system. To lessen this strain, the existing power architecture must be optimized. With the arrival of the age of high speed and power hungry microprocessors, the point of load converter has become a necessity. The power delivery architecture has changed from a centralized distribution box delivering an entire system's power to a distributed architecture, in which a common DC bus voltage is distributed and further converted down at the point of load. Two common distributed bus voltages are 12 V for desktop computers and 48 V for telecommunications server applications. As industry strives to design more functionality into each circuit or motherboard, the area available for the point of load converter is continually decreasing. To meet industries demands of more power in smaller sizes power supply designers must increase the converter's switching frequencies. Unfortunately, as the converter switching frequency increases the efficiency is compromised. In particular, the switching, gate drive and body diode related losses proportionally increase with the switching frequency. This thesis introduces a loss saving self-driven method to drive the secondary side synchronous rectifiers. The loss saving self-driven method introduces two additional transformers that increase the overall footprint of the converter. Also, this thesis proposes a new magnetic integration method to eliminate the need for the two additional gate driver magnetic cores by allowing three discrete power signals to pass through one single magnetic structure. The magnetic integration reduces the overall converter footprint. / Master of Science

The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application to FPGA devices and novel design flow and implementation techniques are proposed. The new methodology and design flow uses a contemporary top down approach using hardware description languages and combines the flexibility of those methods with the efficiency of detailed low level design techniques. As an example of this methodology, a set of floating point arithmetic units consisting of a adder/subtraction, multiplication and division were designed using novel alternative algorithms that significantly outperformed algorithms designed with traditional methods in terms of both size and performance.T hese techniquesu sed were used to form a ToolKit that can accelerateth e design of systems that use floating point units for computer graphics systems. This ToolKit, in combination with a precision investigation methods can be used to generate floating point arithmetic units that have the required precision with minimum required hardware resources. Another emerging technology is that of embedded memory. Recent advancements in semiconductor fabrication processes make it feasible to integrate large amounts of DRAM, SRAM and logic on a single silicon die. This thesis will show the changes in the design flow that are require to take advantage of this new technology. A new embedded logic ToolKit was created that facilitates the exploitation of this technology. Finally, as an example to this methodology, a novel processor oriented towards 3D graphics was designedA. n architecturale xploration driven by novel trace-drivenp erformancea nalysism ethods is detailed that was used to model and tune the processor for the execution of global illumination computer graphics algorithms. The adaptation of these algorithms for execution in our processor is demonstrateda nd the performancea dvantagesth at can be extracteda re shown

The aim of this project is to evaluate the possibility to integrate, in terms of energy, the future Nya Studenternas IP and Uppsala University Hospital. The focus is on integration of thermal energy solutions. To cover the cooling demand a seasonal snow storage and the use of cooling machines is studied. For the heat demand a joint heat storage is investigated which is heated partly with the excess heat from cooling machines. The environmental impact in terms of CO2 emissions is investigated. A conclusion drawn from the project is that the use of district heating and cooling of Nya Studenternas IP and the Uppsala University Hospital could be reduced in several ways by integrating the energy systems of the two facilities. For instance, with the support of a seasonal snow storage and cooling machines for cooling, and heat obtained from the cooling machines for heating, the emissions of CO2 could be reduced with 36% based on a Nordic electricity mixture. Out of the suggested integrated energy solutions the most efficient when it comes to reducing CO2 emissions is cooling and heating through cooling machines with a capacity of reducing the CO2 emissions of 20.6 %.

The punch-through space-charge-limited load (PTSCLL) may be an alternate VLSI design as a high resistance load device. A surface and geometrical study on the PTSCLL device is presented. From this research, it is found out that the dynamic resistance value increases as the surface bias to a negatively voltage. Also, the resistance increases as the channel length and substrate doping increase. But the resistance value decreases as the channel width, junction depth, and overlap oxide thickness increase. Incorporate these design considerations, it can maximize the resistance value of the PTSCLL.

This thesis presents two interface circuits for impedimetric chemical sensors: one for passive chemical sensors and the other for ChemFETs. Both interfaces were fabricated in 0.35μm BiCMOS technology and provide the same output data rate of 1Hz. The interface for passive impedimetric sensors is reconfigurable for performing either resistance or capacitance measurements and provides a fully digital output with less than 81.8μW power consumption at VDD = 2.5V. The interface features a 176dB resistance dynamic range (31.6Ω-200MΩ, <±0.8% nonlinearity, and >40dB SNR) realized with only two sub-ranges to minimize calibration efforts and a 102dB capacitance dynamic range (0.8-1000pF, <±0.2% nonlinearity, and >40dB SNR). The ChemFET interface is a highly versatile system that can generate a wide range of bias voltages (VG up to 9.74V and VD up to 16.3V depending on the measurement modes) and perform either constant voltage or constant current mode measurement. At maximum rated output (VG = 9.74V, VD = 16.3V, and IDS = 15μA), the interface consumes only 2.02μW at VDD = 3.3V and provides analog readout noise levels of 0.0476μARMS at 10μA and 0.503mVRMS for IDS and VT, respectively. Besides attempting versatile system architectures, detailed noise and efficiency analysis were performed for the passive sensor interface and the ChemFET interface, respectively. The noise analysis suggests that different types of noise (correlated or uncorrelated) dominate the noise performance in different measurement ranges and, thus, noise suppression techniques, such as chopper stabilization, correlated double sampling (CDS), and oversampling/averaging, are applied to adequate parts of the interface system. The efficiency analysis of the boost capacitor charger in the ChemFET interface concludes that applying a moderate pulsewidth (200-300ns) to drive the boost converter yields the best efficiencies for charging a capacitor. Compared to interfaces described in the literature, the proposed interface for passive sensors achieves better versatility and wide dynamic range with less number of sub-ranges and power consumption. The proposed interface for ChemFETs achieves wider voltage supply range at very low power level. In-house fabricated chemical sensors, including passive chemical sensors and ChemFETs, were interfaced with the developed circuits and gas-phase chemical measurements with the systems were demonstrated. The novel passive chemical sensor tested in this thesis employs a multi-functional design, which can be configured into either a chemoresistor or a chemocapacitor; the tested ChemFET employs a bottom-gate TFT structure to allow the semiconducting film to interact with the analytes.

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

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