<p>Ved utviklingen av nye produkter er det ønskelig å ha muligheten til å teste produktet for å forsikre korrekt oppførsel. For AHEADs Network on Chip løsning vil en slik testing kreve et skreddersydd testmiljø. Arbeidet i denne oppgaven kartlegger en rekke relevante testfasiliteter, for så å evaluere alle disse med hensyn på implementerbarhet, samt areal- og tidsbegrensninger. Videre er en prioritetsliste opprettet der alle testfasilitetene rangeres etter prioritet. Ut ifra denne prioritetslisten er det implementert en rekke moduler som tilbyr meget nøye trafikksimulering med enten en pseudotilfeldig eller fast bitrate, samt lagring av samtlige pakkers tidsforsinkelse gjennom rutersystemet. Det er også designet en ny arbiter for å bedre utsultingen av den lokale inngangen ved høy pågang på ruteren. Modulene som er designet i denne oppgaven er. • Konfigurerbar trafikkgenerator • Trafikkmonitor • Kontrollmodul for utlesning av data • Arbiter Videre er alle modulene simulert for korrekt oppførsel, samt at systemet er implementert og testet på målplattformen Suzaku-S. Testene viser at testmiljøet er meget anvendelig med hensyn på å simulere kompliserte trafikkbilder, samt gi relevant informasjon og vranglåser og bugs som kan benyttes i videre utvikling av systemet. Testmiljøet er også benyttet til å trafikkplanlegge en videoskalerer, der testmiljøets rolle er å angi om den gitte modulplasseringen tilfredsstiller throughputkravene hver modul har.</p>

<p>In this thesis hardware-software intercommunication in a reconfigurable system has been investigated based on a framework for run time reconfiguration. The goal has been to develop a fast and flexible link between applications running on an embedded processor and reconfigurable accelerator hardware in form of a Xilinx Virtex device. As a start the link was broken down into hardware and software components based on constraints from earlier work and a general literature search. A register architecture for reconfigurable modules, a reconfigurable interface and a backend bridge linking reconfigurable hardware with the system bus were identified as the main hardware components whereas device drivers and a hardware operating system were identified as software components. These components were developed in a bottom-up approach, then deployed, tested and evaluated. Synthesis and simulation results from this thesis suggest that a hybrid register architecture, a mix of shift based and addressable register architecture might be a good solution for a reconfigurable module. Such an architecture enables a reconfigurable interface with full duplex capability with an initially small area overhead compared to a full scale RAM implementation. Although the hybrid architecture might not be very suitable for all types of reconfigurable modules it can be a nice compromise when attempting to achieve a uniform reconfigurable interface. Backend bridge solutions were developed assuming the above hybrid reconfigurable interface. Three main types were researched: a software register backend, a data cache backend and an instruction and data cache backend. Performance evaluation shows that the instruction and data cache outperforms the other two with an average acceleration ratio of roughly 5-10. Surprisingly the data cache backend performs worst of all due to latency ratios and design choices. Aside from the BRAM component required for the cache backends, resource consumption was shown to be only marginally larger than a traditional software register solution. Caching using a controller in the backend-bridge can thus provide good speedup for little cost as far as BRAM resources are not scarce. A software-to-hardware interface has been created has been created through Linux character device driver and a hardware operating system daemon. While the device drivers provide a middleware layer for hardware access the HWOS separates applications from system management through a message queue interface. Performance testing shows a large increase in delay when involving the Linux device drivers and the HWOS as compared to calls directly from the kernel. Although this is natural, the software components are very important when providing a high performance platform. As additional work specialized cell handling for reconfigurable modules has been addressed in the context of a MPEG-4 decoder. Some light has also been shed on design of reconfigurable modules in Xilinx ISE which can radically improve development time and decrease complexity compared to a Xilinx Platform Studio flow. In the process of demonstrating run time reconfigurations it was discovered that a clock signal will resist being piped through bus macros. Also broken functionality has been shown when applying run time reconfiguration to synchronous designs using the framework for self reconfiguration.</p>

<p>This paper contains the analysis, development, production and testing of a surveillance system for the monitoring of the MKDG, a high voltage pulse kicker in the MKD-system. The MKD-system is a part of the LHC Beam Dump System situated at point 6 in the LHC. The surveillance is active whenever the MKDs are operational. The system is reporting any deviations from normal behaviour and runs an extensive analysis of the MKDG whenever there is a beam dump. The results are checked before a new run in the LHC can be initiated. The final result is a working prototype which monitors and analyzes the MKDG and communicates the results to a PLC. The accomplished resolution is 10 bits for all six channels and this is acceptable.</p>

<p>This Master's thesis reports the verification planning and verification process of a Verilog RTL model. Modern verification techniques like constrained randomization, assertions, functional coverage analysis and object orientation are demonstrated on an AES RTL model. The work of this thesis was naturally divided in three phases: First, a phase of literature studies to get to know the basics of verification. Second, the creation of a verification plan for the selected module. Third, implementation of the testbench, and simulation tasks. The verification plan created states the goals for the simulation. It also states plans for details about the testbench, like architecture, stimuli generation, random- ization, assertions, and coverage collection. The implementation was done using the SystemVerilog language. The testbench was simulated using the Synopsys VCS ver- ification software. During simulation, coverage metrics were analyzed to track the progress and completeness of the simulation. Assertions were analyzed to check for errors in the behavior during simulation. The analysis carried out revealed high code coverage for the simulations, and no major errors in the verified module.</p>

<p>3D graphic accelerators are often limited by their floating-point performance. A Graphic Processing Unit (GPU) has several specialized floating-point units to achieve high throughput and performance. The floating-point units consume a large part of total area, and power consumption, and hence architectural choices are important to evaluate when implementing the design. GPUs are specially tuned for performing a set of operations on large sets of data. The task of a 3D graphic solution is to render a image or a scene. The scene contains geometric primitives as well as descriptions of the light, the way each object reflects light and the viewer position and orientation. This thesis evaluates four different pipelined, vectorized floating-point multipliers, supporting 16-bit, 32-bit and 64-bit floating-point numbers. The architectures are compared concerning area usage, power consumption and performance. Two of the architectures are implemented at Register Transfer Level (RTL), tested and synthesized, to see if assumptions made in the estimation methodologies are accurate enough to select the best architecture to implement given a set of architectures and constraints. The first architecture trades area for lower power consumption with a throughput of 38.4 Gbit/s at 300 MHz clock frequency, and the second architecture trades power for smaller area with equal throughput. The two architectures are synthesized at 200 MHz, 300 MHz and 400 MHz clock frequency, in a 65 nm low-power standard cell library and a 90 nm general purpose library, and for different input data format distributions, to compare area and power results at different clock frequencies, input data distributions and target technology. Architecture one has lower power consumption than architecture two at all clock frequencies and input data format distributions. At 300 MHz, architecture one has a total power consumption of 1.9210 mW at 65 nm, and 15.4090 mW at 90 nm. Architecture two has a total power consumption of 7.3569 mW at 65 nm, and 17.4640 mW at 90 nm. Architecture two requires less area than architecture one at all clock frequencies. At 300 MHz, architecture one has a total area of 59816.4414 um^2 at 65 nm, and 116362.0625 um^2 at 90 nm. Architecture two has a total area of 50843.0 um^2 at 65 nm, and 95242.0469 um^2 at 90 nm.</p>

<p>Devices such as microcontrollers are often required to operate across a wide range of voltage and temperature. Delay variation in different temperature and voltage corners can be large, and for deep submicron geometries delay faults are more likely than for larger geometries. This has made delay fault testing necessary. Scan testing is widely used as a method for testing, but it is slow due to time spent on shifting test vectors and responses, and it also needs modification to support delay testing. This assignment is divided into three parts. The first part investigates some of the effects in deep submicron technologies, then it looks at different fault models, and at last different techniques for delay testing and BIST approaches are investigated. The second part suggests a design for a test chip, including a circuit under test (CUT) and BIST logic. The final part investigates how the selected BIST logic can be used to reduce test time and what considerations needs to be made to get a optimal solution. The suggested design is a co-processor with SPI slave interface. Since scan based testing is commonly used today, STUMPS was selected as the BIST solution to use. Assuming that scan already is used, STUMPS will have little impact on the performance of the CUT since it is based on scan testing. During analysis it was found that several aspects of the CUT design affects the maximum obtainable delay fault coverage. It was also found that careful design of the BIST logic is necessary to get the best fault coverage and a solution that will reduce the overall cost. The results shows that a large amount of time can be saved during test by using BIST, but since the area of the circuit increases due to the BIST logic it necessarily don’t mean that one will reduce cost on the overall design. Whether or not a BIST solution will result in reduced cost will depend on the complexity of the circuit that is tested, how well the BIST logic fits this circuit, how many internal scan chains can be used, and how fast scan vectors can be applied under BIST. In this case it looks like the BIST logic is not well suited to detect the random hard to detect faults. This results in a large amount of top up patterns. This combined with the large area of the BIST logic makes it unlikely that BIST will reduce cost of this design.</p>

<p>In this project the focus has been on developing an MPEG transcoder that can be used as a demonstration module for the AHEAD system, Ambient Hardware: Embedded Architecture on Demand. AHEAD is a collaboration project between NTNU and SINTEF in Trondheim that is aiming to develop a method of doing run-time reconfiguration of hardware. The AHEAD system will in the future use an FPGA in a tag that is able to reconfigure itself with hardware description that it receives from a hand-held device, e.g. a PDA, or downloads from the Internet. The tag will then be able to be operating as a co-processor for hand-held devices in the vicinity of the tag. Consequently, since the hand-held devices avoid doing some of the heavy processing of the video stream, the power consumption in the hand-held device will be decreased. The MPEG transcoder in this report consists of two parts, an MPEG-4 decoder and an MPEG-2 encoder, that are connected and form a complete transcoder. The MPEG-4 decoder was designed in software in the pre-project to this Master thesis and was in this Master thesis designed in hardware. The MPEG-2 encoder was partially designed by the former students Rognerud and Rustad, but was not working as required and had to be modified to a large extent. In this project the MPEG-4 decoder has been designed from scratch, and the MPEG-2 encoder has been modified in such a way that it operates as specified in the MPEG-2 standard. The first part that was designed was the MPEG-4 decoder. This was due to the experience on that part from the pre-project and that it is the first part of the transcoder. Also, it was useful to produce input data to the encoder. Secondly, the MPEG-2 encoder was modified to operate as required. However, the amount of time spent on finding the errors and resolve them in this part was larger than assumed in the beginning of the project. There was found a way to downscale the resolution of a video in the frequency domain and thus, the Inverse Discrete Cosine Transform, IDCT, and Discrete Cosine Transform, DCT, modules were not needed in the design of the MPEG transcoder. However, the resolution scaler has not been designed in this project, but should be a part of the MPEG transcoder in the future. This should be done to further decrease the power consumption in the hand-held device. In other words, the resolution scaler would be a very important module of the MPEG transcoder and should be implemented in the future MPEG transcoder to make it more beneficial for use in the AHEAD system. During testing and verification, both the MPEG-4 decoder and the MPEG-2 encoder were found to be functioning as specified by the MPEG standards. A video was decoded from MPEG-4, transcoded to MPEG-2 and recognized as an MPEG-2 video that could be displayed in several media players showing good video quality. The results from the synthesis show that the complete MPEG transcoder would use 84% of the available resources on the FPGA that is available for experimental purposes in this project. Also, it shows that the designed MPEG transcoder could operate on a clock frequency of 54 MHz. This results in an MPEG transcoder that is capable of transcoding videos of at least full DVD quality, 720 x 576 pixels, at run-time, which is thought to be sufficient for most cases in AHEAD. Additionally, the transcoder would for most cases be able to transcode HD video of 1280 x 720 resolution, however this is depending on the degree of compression and the nature of the incoming MPEG-4 video. It is concluded in this Master thesis that it has been designed, tested and verified an MPEG transcoder that transcodes MPEG-4 video to MPEG-2 video. The MPEG transcoder is capable of handling at least DVD quality video, which should be sufficient for most cases in AHEAD. There has not been focused on incorporating the transcoded video in a transport stream at run-time in this project. However it is recommended to do so in a future transcoder system and the interface of the MPEG transcoder in this project has been described to make this easier. Also, an article explaining a method for doing resolution scaling in the frequency domain has been proposed. It has further been concluded that the MPEG transcoder designed in this project is a huge step toward having an MPEG transcoding system that can operate in the future AHEAD system. Additionally, it has been experienced that reusing other designers modules sometimes can be less convenient since the increased amount of time spent on debugging can exceed the extra time spent on designing it from scratch. This is because the self designed modules tend to be easier to debug.</p>

<p>The main idea behind this thesis was to optimize the multipliers in a finite impulse response (FIR) filter. The project was chosen because digital filters are very common in digital signal processing and is an exciting area to work with. The first part of the text describes some theory behind the digital filter and how to optimize the multipliers that are a part of digital filters. The substantial thing to emphasize here is the use of Canonical Signed Digits (CSD) encoding. CSD representation for FIR filters can reduce the delay and complexity of the hardware implementation. CSD-encoding reduces the amount of non-zero digits and will by this reduce the multiplication process to a few additions/subtractions and shifts. In this thesis it was designed 4 versions of the same filter, that was implemented on an FPGA, where the substantial and most interesting results were the differences between coefficients that was CSD-encoded and coefficients that was represented with 2's complement. It was shown that the filter version that had CSD-encoded coefficients used almost 20% less area then the filter version with 2's complement coefficients. The CSD-encoded filter could run on a maximum frequency of 504,032 MHz compared the other filter that could run on a maximum frequency of 249,123 MHz. One of the filters that was designed was designed using the * operator in VHDL, that proved to be the most efficient when it came to the use of number of slices and speed. The reason for this was because an FPGA has built-in multipliers, so if one has the opportunity to use the multiplier they will give the best result instead of using logic blocks on the FPGA It was also discussed a filter that has the ability to change the coefficients at run-time without starting the design from the beginning. This is an advantage because a constant coefficient multiplier requires the FPGA to be reconfigured and the whole design cycle to be re-implemented. The drawback with the dynamic multiplier is that is uses more hardware resources.</p>

<p>Flash ADCs with resolutions from 3 to 5 bits have been implemented on a transistor level. These ADCs are to be incorporated as the backend of a higher resolution Pipeline ADC. The motivation for this work has been to see how much the resolution of this backend can be increased before the power consumption becomes to high. This is beneficial in Pipeline ADCs because the number of Pipeline stages is reduced so that the throughput delay of the Pipeline ADC is also reduced. All the Flash ADCs are implemented with the same Capacitive Interpolation-technique. This technique was found to have several benificial properties as opposed to other power saving techniques applied to Flash ADCs in a project assignment done prior to this thesis. The results of the simulations show that the resolution of the backend can be increased to 5 bits both in terms of power and other static and dynamic performance parameters.</p>

<p>A found state of the art Continuous Time Sigma Delta ADC is modelled and simulated for the presence of nonidealities. A comparison between two Excess Loop Delay compensation techniques is done, the digital differentiation technique was found to have lower swing at the last integrator, and did not need a gain-bandwidth induced delay sensitive summing amplifier. The detrimental influence of clock jitter is shown. Different DAC linearization techniques are discussed, the DWA algorithm was simulated and found to be the best choice for linearizing the DACs. Through high level modeling in Simulink and verification in the Cadence framework specifications for each building block was determined, a final simulation resulted in a SNDR of 76.3 dB.</p>