<p>Partial self reconfigurable hardware has not yet become main stream, even though the technology is available. Currently FPGA manufacturer like Xilinx has FPGA devices that can do partial self reconfiguration. These and earlier FPGA devices were used mostly for prototyping and testing of designs, before producing ASICS, since FPGA devices was to expensive to be used in final production designs. Now as prices for these devices are coming down, it is more and more normal to see them in consumer devices. Like routers and switches where protocols can change fast. Using a FPGA in these devices, the manufacturer has the possibility to update the device if there are protocol updates or bugs in the design. But currently this reconfiguration is of the complete design not just modules when they are needed. The main problem why partial self reconfiguration is not used currently, is the lack of tools, to simplify the design and usage of such a system. In this thesis different aspects of partial self reconfiguration will be evaluated. Current research status are evaluated and a proof of concept incorporating most of this research are created. Trying to establish a framework for partial self reconfiguration on a FPGA. In the work the Suzaku-V platform is used, this platform utilizes a Virtex-II or Virtex-IV FPGA from Xilinx. To be able to partially reconfigure these FPGA's the configuration logic and configuration bitstream has been researched. By understanding the bitstream a program has been developed that can read out or insert modules in a bitstream. The partial reconfiguration in the proof of concept is controlled by a CPU on the FPGA running Linux. By running Linux on the CPU simplifies many aspects of development, since many programs and communication methods are readily available in Linux. Partial self reconfiguration on a FPGA with a hard core powerPC running Linux is a complicated task to solve. Many problems were encounter working with the task, hopefully were many of these issues addressed and answered, simplifying further work. Since this is only the beginning, showing that it is possible and how it can be done, but more research must be done to further simplify and enhance the framework.</p>

<p>This assignment has been given by Defence Communication (DC) which is a division of Kongsberg Defence and Aerospace(KDA). KDA develops amongst other things military radio equipment for communication and data transfer. In this equipment there is use of digital logic that performes amongst other things integer and fixed point division. Current systems developed at KDA uses both application specific integrated circuit (ASIC) and field programmable gate arrays (FPGA) to implement the digital logic. In both these technologies it is implemented circuit to performed integer and fixed point division. These are designed for low latency implementations. For future applications it is desire to investigate the possibility of implementing a high throughput pipelined division circuit for both 16 and 64 bit operands. In this project several commonly implemented division methods and algorithms has been studied, amongst others digit recurrence and multiplicative algorithms. Of the studied methods, multiplicative methods early stood out as the best implementation. These methods include the Goldschmidt and Newton-Raphson method. Both these methods require and initial approximation towards the correct answer. Based on this, several methods for finding an initial approximation were investigated, amongst others bipartite and multipartite lookup tables. Of the two multiplicative methods, Newton-Raphsons method proved to give the best implementation. This is due to the fact that it is possible with Newton-Raphsons method to implement each stage with the same bit widths as the precision out of that stage. This means that each stage is only halve the size of the succeeding stage. Also since the first stages were found to be small compared to the last stage, it was found that it is best to use a rough approximation towards the correct value and then use more stages to achieve the target precision. To evaluate how different design choices will affect the speed, size and throughput of an implementation, several configurations were implemented in VHDL and synthesized to FPGAs. These implementations were optimized for high speed whit high pipeline depth and size, and low speed with low pipeline depth and size. This was done for both 16 and 64 bits implementations. The synthesizes showed that there is possible to achieve great speed at the cost of increased size, or a small circuit while still achieving an acceptable speed. In addition it was found that it is optimal in a high throughput pipelined division circuit to use a less precise initial approximation and instead use more iterations stages.</p>

<p>A comparator-based switched capacitor integrator for use in a Delta Sigma ADC has been designed. Basic theory about comparator-based circuits has been presented and design equations have been developed. The integrator had a targeted performance of a bandwidth of 1.5MHz with a SNR of 80dB. Due to the lack of a complete modulator feedback system, the integrator was simulated in open-loop. For the integrator not to saturate in open-loop, an overshoot calibration circuit was enabled during the simulation. This resulted in a severe deterioration of the integrated signal. The results are therefore significantly lower than expected, with a SNR of about 39dB but can be expected to be better in a closed-loop simulation. The power consumption of the implemented modules is 0.43mW. However, this is without several modules which were implemented as ideal.</p>

<p>Energy efficiency in embedded processors is of major importance in order to achieve longer operating time for battery operated devices. In this thesis the energy efficiency of a microcontroller based on the open source ZPU microprocessor is evaluated and improved. The ZPU microprocessor is a zero-operand stack machine originally designed for small size FPGA implementation, but in this thesis the core is synthesized for implementation with a 180nm technology library. Power estimation of the design is done both before and after synthesis in the design flow, and it is shown that power estimates based on RTL simulations (before synthesis) are 35x faster to obtain than power estimates based on gate-level simulations (after synthesis). The RTL estimates deviate from the gate-level estimates by only 15% and can provide faster design cycle iterations without sacrificing too much accuracy. The energy consumption of the ZPU microcontroller is reduced by implementing clock gating in the ZPU core and also implementing a tiny stack cache to reduce stack activity energy consumption. The result of these improvements show a 46% reduction in average power consumption. The ZPU architecture is also compared to the more common MIPS architecture, and the Plasma CPU of MIPS architecture is synthesized and simulated to serve as comparison to the ZPU microcontroller. The results of the comparison with the MIPS architecture shows that the ZPU needs on average 15x as many cycles and 3x as many memory accesses to complete the benchmark programs as the MIPS does.</p>

<p>A high performance sound card is designed and implemented using a USB enabled microcontroller and an external dataconverter. Data is retrieved either via USB or S/PDIF. The sampling clock is generated by a precision clock synthesizer. This is programmable and can be adapted to different sampling rates of USB data. The system supports 24 bit, 192 kHz audio. Signal attenuation is performed through a relay based stepped voltage divider with constant output impedance. 64 dB attenuation in steps of 1 dB is available. An extensive power supply is made to support the range of required voltages. The signal to noise ratio of the power supply was measured to be 93 dB in the audio frequency band. The microcontroller has been programmed to handle the USB communication and provision of control signals for the system. The whole system is assembled on PCBs and tested. The audio performance measurements show a dynamic range of 105 dB, measured at the system output in a noisy environment. The total harmonic distortion plus noise was 0.0011 %.</p>

<p>Cryptographic algorithms, like the Advanced Encryption Standard, are frequently used in todays electronic appliances. Battery operated devices are increasingly popular, creating a demand for low energy solutions. As a microcontroller is incorporated in virtually all electronic appliances, the main objective in this thesis is to evaluate possible hardware implementations of AES and implement a solution optimized for low energy consumption, suited for incorporation in a microcontroller. A good cost/performance balance is also a design goal. An existing solution based on a 32 bit architecture with support for 128 bit keys was chosen as a basis and altered in order to lower area and energy consumption. The alterations yielded a 13.6% area reduction as well as 14.2% and 3.9% reduction in energy consumption in encryption and decryption mode, respectively. In addition to alterations in the datapath, low energy techniques like clock gating and numerical strength reduction has been applied in order to further lower the energy consumption. The proposed architecture was also extended in order to accommodate 256 bit keys. Although this increased the area by 9.2%, the power consumption was still reduced by 7.6% and 1.3% in en- and decryption, compared to the architecture chosen as basis. As AES is an algorithm which easily can be parallelized, a high throughput solution utilizing a 128 bit datapath was implemented. This AES module is able to process 372.4 Mbps at an operating frequency of 32 Mhz and is based on the same architecture as the 32 bit datapath solution. In addition, this implementation yielded excellent energy per encryption figures, 24.5% lower than the 32 bit solution. The alternative to performing AES in a dedicated hardware module is to perform it using software. In order to have a basis for comparison, a software solution optimized for 32 bit architectures was implemented. Simulations show that the energy consumption attained when performing AES in the proposed hardware module is approximately 2.3% of what a software solution would use. In addition, the throughput is increased by a factor of 25. The architecture proposed in this thesis combines relatively high throughput with modest demands to area and low energy per encryption.</p>

<p>This report describes the assessment and design of a 10 dBm 2.4 GHz CMOS PA including driver stage. The PA is designed in a 0.18 um CMOS technology. A three stage PA has been designed due to the high voltage gain needed. Class F has been chosen for the output stage. An output filter short-circuiting the second harmonic frequency and reflecting the third harmonic frequency is used to obtain the near-square drain voltage that is characteristic to class F. A lowered supply voltage of 0.9 V is used to avoid exceeding the transistor break-down voltage of 2 V. The typical output power achieved is 10.2 dBm. The drain efficiency of the output stage is 47.7 %, and the PAE of the entire PA is 30.5 %. The final layout excluding bonding pads consumes an area of 0.66 mm2, including four internal inductors consuming a total of 0.59 mm2. The PAE obtained is higher than those of a selection of recently published PAs that are comparable in technology, frequency and output power.</p>

<p>This paper reports on the modeling and simulation of a continuous-time delta-sigma analog to digital converter (ADC) in VHDL AMS. The ADC is intended for use in a microcontroller and is therefore underlying restrictions on power consumption. Continuous-time delta-sigma architectures are well known for their good low-power capabilities compared to discrete-time realizations. This is due to their reduced demands to the gain bandwidth product (GBW) of the internal amplifiers in the ADCs. Continuous-time ADCs often operate with GBWs in the range of the sampling frequency, fs. The ADC presented in this work is also employing a previously reported compensation technique which ideally allows the GBW to be reduced further >20 times of this. Considering that the current drain in the amplifiers usually is proportional with GBW, this could be a promising power saving technique. The work focuses on the development of two similar models of a 2-order continuous-time delta-sigma ADC in VHDL-AMS, where one of the ADCs is using the compensation technique. The main purpose is to see how the compensated ADC is affected by nonidealities such as GBW-variation, finite amplifier gain, RC-product variation, excess loop delay and finite DAC slew rate compared to the performance of the noncompensated ADC. The required accuracy for the modeled ADCs is 62dB Signal to Noise and Distortion Ratio (SNDR), thus an appropriate oversampling ratio (OSR) also must be found. The simulations show that the compensated ADC has similar performance as the noncompensated ADC operating with GBW=10*fs when subject to the different nonidealities. With an OSR=64 it stays within the accuracy specification for GBWs >= 0.05*fs This is however only valid if actual GBW stays within +-40% of the GBW compensated for. For larger deviations, especially lower GBW values, the SNDR drops rapidly. It is also shown that the internal signal swing in the ADC is reduced for low GBW values. This may limit the practical achievable SNDR when subject to circuit noise. If these potential drawbacks are circumvented, the compensation technique could lead to a further decrease of the power consumption in continuous-time delta-sigma ADCs.</p>

<p>A 64-modulus prescaler operating at 5.8 GHz has been designed in a 0.18 μm CMOS process. The prescaler uses a four-phase high-speed ÷4 circuit at the input, composed of two identical cascaded ÷2 circuits implemented in pseudo-NMOS. The high-speed divider is followed by a two-bits phase switching stage, which together with the input divider forms a ÷4/5/6/7 circuit. The phase switching stage is mostly implemented in complementary CMOS. After this follows four identical ÷2/3 cells with local feedback, also implemented in complementary CMOS. Other architectural approaches are also described and tried out. An architecture based solely the ÷2/3 cells with local feedback is presented. The ÷2/3 cells were implemented and simulated, and worked up to 2.3 GHz. An alternative high-speed divider based on an inverter ring interrupted by transmission gates is also described. Simulations showed that a divider using pseudo-NMOS inverters and CMOS transmission gates operated well and gave out four signals evenly spaced in phase at a input frequency of 4.8 GHz.</p>

<p>Software defined radio (SDR) is an emerging trend of radio technology. The idea is basically to move software as close to the antenna of a radio system as possible, to improve flexibility, adaptability and time-to-market. This thesis covers the description of a DSP architecture especially optimized for modulation / demodulation algorithms of low-complexity, low-power radio standards. The DSP allows software processing of these algorithms, making SDR possible. To make the DSP competitive to traditional ASIC modems, tough constraints are given for area and power consumption. Estimates done to indicate the power consumption, area and computational power of the DSP, shows that a software implementation of the studied physical layer should be possible within the given constraints.</p>