When new transistor technology is used in a microcontroller design, the transistors become smaller. They cannot withstand the same voltages as older technology, because of their size. The automotive industry still uses 5V as a standard voltage, and the automotive industry is a major costumer for microcontroller companies. The microcontroller must therefore be able to use5V. This must be done without the need of external voltage regulator. To still be a supplier to the automotive industry, the AVR needs to be able to withstand voltages up to 5.5V. The main problem with the new transistor technology is the leakage currents. Traditionally, the CMOS devices have used power only when during switching of logical levels. This is no longer true, since the leakage currents have become so large. When using new transistor technology, the dynamic power usage will be reduced, but the total power usage will be increased, if nothing is done to prevent it. One solution to this is to make a multiple power domain microcontroller. The idea is that one power domain can withstand voltages up to 5.5V. The microcontroller then uses an internal voltage regulator to scale down the voltage to a suitable level. The low voltage area will then have a suitable voltage level, which reduces both the dynamic- and leakage power usage. The different voltage domains uses different clock sources, so communicating between them requires both level shifters to deal with the different voltage levels, and synchronization logic to prevent metastability. This assignment uses two voltage domains, VIO and VCORE. Since voltage regulators are quite inefficient, it is most efficient to use only two domains. The VCORE domain contains most of the digital logic of the microcontroller, such as the CPU, SRAM and timers. This domain uses a high-speed clock source, and a VCORE data bus to communicate between each other. To communicate with the VIO domain, the data bus is connected to the VIO data bus through an asynchronous communication scheme block. This is because the VIO domain uses a low speed clock source. The usage of individual clock sources prevents clock skew problems that may occur when passing level shifters, and there is power saving by using only a low speed clock source on the VIO domain. The VIO domain contains the Power Management Unit (PMU). The PMU shall control the power usage of the microcontroller. During active mode, the PMU can set unused modules in sleep mode, or shut them completely off. Most of the power savings are during sleep mode though. This is because a microcontroller such as the AVR spends most of the time in sleep mode. To reduce the power usage in sleep mode, the leakage currents needs to be reduced. The best way of doing so is to disconnect the power from the circuits. If the voltage regulator is disconnected, and all the inputs are set to high impedance, the VCORE domain is completely disconnected from the power, and uses absolutely no power. An asynchronous wake up circuit is designed to make it possible to wake up the microcontroller from a sleep mode without the usage of synchronized digital logic. Then the low frequency oscillator can be turned off, and even more power is saved. The major disadvantage of the multiple power domain solution is the start up time from a sleep mode. If the power to the low voltage area is disconnected, the start up requires that all the capacitors become charged before the chip can start running again. The oscillator is shut off, and it takes time to stabilize the oscillator. Especially since the oscillator requires some stability in the voltage, and the voltage may not stable until the capacitors are charged. Simulations shows that the multiple power domain solution has great potential of power saving. The proposed asynchronous wake up circuit uses only 1.2275nA. This is significantly smaller than the AVR uses in the deepest sleep mode today. To get a secure microcontroller, a reset circuit has to be on to be able to reset the AVR if necessary. The power usage of the reset circuit used today is confidential Atmel information, and cannot be published in this assignment. By looking at the data sheet of a pico power circuit of the AVR, the ATmega329p, one can see that in the deepest sleep mode, the microcontroller uses 40nA at 1.8V. By assuming that the reset circuit does not use more that half of this current, the total amount of power that saved during a sleep mode by using the multiple power domain solution is about 47%.

Wireless data networks have seen rapid growth and deployment in the recent years, replacing traditional wired data networks. WesternGeco is currently using a traditional wired data network in the land seismic operations to connect the Head Vibrator with the Recording Truck. The thesis provides a survey of the most important wireless data network technologies available. A comparison between them is done in order to determine the best suited for WesternGeco’s communication mechanism. The study has lead to the conclusion that IEEE 802.11g is the most suited technology. Through the use of high gain antennas, modification of MAC layer parameters and the proper channel allocation, the suggested solution is capable of responding what WesternGeco needs.

Today Lithium Ion batteries are extensively used in all kinds of electronic equipment due to its superior properties. However, Lithium Ion batteries need to have all the individual cells monitored to ensure the safety and long life time. This master thesis' objective is to design a managing system for a ten cell Lithium Ion battery with an Atmel AVR microcontroller. The main challenge was to scale down the high voltage level a 10 cell battery has and still maintain accuracy when reading this voltage with the AVR. This was solved by using current sense monitors which can handle large common mode voltages. Hardware was made to show proof of concept. It was found that the scaling circuitry had an accuracy of 46mV. In competition with other single chip devices, some other methods have to be found. The design in this thesis is physically too large and too expensive to be of any commercial use. However some other methods worth looking into have been proposed in the last chapter.

High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power. In this thesis, some research is done in how to optimize a software and hardware development for ultra low power consumption. A cardiac beat detector algorithm is implemented in ANSI C, and optimized for low power consumption, by using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies. This processor is optimized further for ultra low power consumption by applying application specific hardware, and by using several hardware power optimization techniques. A general processor and the optimized processor has been mapped on a chip, using a 90 nm low power TSMC process. Information about power dissipation is extracted through netlist simulation, and the results of both processors have been compared. The optimized processor consume 55% less average power, and the duty cycle of the processor, i.e., the time in which the processor executes its task with respect to the time budget available, has been reduced from 14% to 2.8%. The reduction in the total execution cycle count is 81%. The possibilities of applying power gating, or voltage and frequency scaling are discussed, and it is concluded that further reduction in power consumption is possible by applying these power optimization techniques. For a given case, the average leakage power dissipation is estimated to be reduced by 97.2%.

Digital multipliers are an important part of most of digital computation systems, such as microcontrollers and microprocessors. Multiplication operation is a quite complex task, thus there is many different solution varying in area, speed and power consumption. An important notice is that multipliers often are a part of critical path of a system which makes them especially important for these factors. During last decade, power efficiency has become an important issue in digital design and a lot of design methods has been created and investigated to meet this subject. It is a known fact that most of power consumed by arithmetic circuit is dissipated by hazards and toggles (up to 75%), that do not bring any information to final result. The method of evaluating the amount of spurious switching and its effect on power dissipation is investigated here. This thesis aims to find a method to estimate switching characteristics and its effect on power dissipation of eight supplied multipliers given in form of HDL net-list with some software overhead. As switching generally stands for majority of power consumption in digital CMOS circuits, this effect gives also good indication of overall power dissipation. One of the difficulties in estimating average power and transition density is pattern dependency problem. The method based on Monte Carlo technique is used where an adequate accuracy is obtained within moderate time and resource usage. Three of investigated multipliers are net-lists created by using methodology developed in [21]. These are synthesized and laid out in the technology used by Atmel Norway. The amount of logical state changes is compared from pre- and post- synthesis net-lists. The technology mapped net-lists are also examined for power consumption to see the connection between switching and dynamic power dissipation. The fan-out delay model used to estimate total toggling gives a good approximation of circuit properties; it is however too simple to give a good estimate of spurious toggling inside the circuit and its effect on power consumption. The same estimation technique is used to investigate a DesignWare circuit (DW02) which is an industrial approach of building fast and power efficient multipliers. The results show that this is the most power effective solution among the examined circuits (45-47% less than the most power efficient circuit from [21]) It is also a solution with smallest amount of hazards during a multiplication operation (38-52%). A circuit generated by module generation software (ModGen) is also investigated. This solution is quite power efficient, it has however largest amount of power dissipated by the spurious toggling (62-68%). It is also noticed that transition density and what follows the power dissipation in strongly dependent on the process, temperature and voltage variation. In fact the higher temperature gives reduction in power consumption.

This thesis will seek to design a capacitive touch sensor that uses as little power as possible while still having decent performance. The study will start by discussing oscillators and find that relaxation oscillators with a frequency dependent on an RC-circuit is of greatest interest. Thorough simulations and theory will show that it is power efficient for the RC-circuit to oscillate between two voltage levels close to the supply voltage. It will also show that it is only the resistance that affect the power dissipation in the RC-circuit. A Finite State Machine that monitors changes in the period of the oscillator is described and designed. It uses two IIR filters to reject noise from the oscillator and provide an average over time the input can be compared to. A prototype is built and tests establish that both the oscillator and FSM behave as expected. It is found that the response time of the FSM can be stated in sampling periods and that lower bit lengths give faster response time. Power estimations are done and it is found that the FSM uses two orders of magnitude less power than the oscillator. The full design is compared to a low power capacitive touch system currently on the market. Power estimations indicate that the design proposed uses an order of magnitude less power than the commercial implementation it is compared with. The results also indicate that the proposed design has a potential for even more power optimization.

This thesis explores the ability of the proprietary Texas Instruments embedded 16 bits RISC microprocessor, NanoRisc, to process common lossless compression algorithms, and propose extensions in order to increase its performance on this task. In order to measure performance of the NanoRisc microprocessor, the existing software tool chain was enhanced for profiling and simulating the improvements, and three fundamentally different adaptive data compression algorithms with different supporting data structures were implemented in the NanoRisc assembly language. On the background of profiling results, some enhancements were proposed. The new enhancements improved throughput of the three implemented algorithms by between 18% and 103%, and the code sizes decreased between 6% and 31%. The bit field instructions also reduced RAM access by up to 53%. The enhancements were implemented in the NanoRisc VHDL model and synthesized. Synthesis reports showed an increase in gate count of 30%, but the whole NanoRisc core is still below 7k gates. Power consumption per MIPS increased by 7%, however reduced clock cycle count and memory access decreased the net power consumption of all tested algorithms. It is also shown that data compression with the NanoRisc prior to transmission in a low power RF transceiver may increase battery lifetime 4 times. Future work should include a comprehensive study of the effect of the proposed enhancements to more common applications for the NanoRisc microprocessor.

A 90nm CMOS technology has been characterized on the basis of IV and CV measurements. This was feasible by means of a state of the art probe station and measurement instrumentation, capable of measuring current and capacitance in the low fA and fF area respectively. From IV results it was found that the static power consumption is an increasing challenge as the technology is scaled down. The IV measurements also showed the impact from small-channel effects, which was not as prominent as expected. Investigation of literature has resulted in a methodology for accomplishing accurate CV measurements on thin-oxide transistors. By using extraction methods on the capacitance measured, key parameters have been obtained for the CMOS technology. Some of the extracted results suffer however from the choice of test setup.

Power consumption becomes more important as more devices becomes embedded or battery dependant. Multipliers are generally complex circuits, consuming a lot of energy. This thesis uses Sand's multiplier generator, made for his master thesis, as a basis. It uses tree structures to perform the multiplication, but does not take power consumption into account when generating a multiplier. By adding power optimization to the generator, multipliers with low energy consumption could be made automatically. This thesis adds different reduction tree algorithms (Wallace, Dadda and Reduced Area) to the program, and an optimal algorithm might be found. After the multiplier tree generation, an optimization step is performed, trying to exploit the delay and activity characteristics of the generated multiplier. A simplified version of Oskuii's algorithm is used. To be able to compare the different algorithms with each other, a pre-layout power estimation routine was implemented. The estimator is also used by the post-generation optimization. Since accuracy is important in an estimator, the delay through a multiplier was also investigated. Taking the previous mentioned steps into account, we are able to get a 10% decrease in overall power reduction in a 0,18/0,15um CMOS technology, reported by "IC Compiler". Delay characteristics of a multiplier is also supplied, and can be used by other power estimators. This thesis shows how to achieve less power consumption in multipliers. It also shows that the delay model is important for estimation purposes, and how an estimator is used to optimize a multiplier. The findings in this thesis can be used as is, or be used as a basis for further study.

Denne rapporten bygger på arbeidet som er gjort i forbindelse med en FPGA plattform for AHEAD prosjektet. Teori og arbeid i rapporten er bygd rundt den valgte FPGA utviklingsplattformen Suzaku-S. Rapporten begynner med litt beskrivelse av AHEAD og systemet, samt en motivasjon med forklaring av hva dette kan brukes til. Videre går en inn på litt teori om hvilke krav som stilles til slike systemer og hvilke av kravene som er tilfredsstilt ved valget av den nevnte utviklingsplattform. Rapporten inneholder videre en dokumentasjon på arbeidet som er utført og en forklaring på hvordan den ferdige versjon 1 av AHEAD plattformen virker. Resultatet er altså en ferdig FPGA-plattform uten ekstern mikroprosessor, der en heller valgte å bruke FPGAens interne prosessor. Plattformen inngår i en verktøykjede som inneholder utviklings-PC, FPGA-plattform og http-server. Mikroprosessoren i FPGAen kjører en tilpasset uClinux som operativsystem. uClinux er tilpasset spesielt denne prosessoren og dette systemet, og er kompilert på utviklings-PCen. FPGA-plattformen som er implementert er en html/script-basert AHEAD-server. Det vil si at plattformen bruker html kode og en webserver som grensesnitt, samt linker til script for å lage funksjonalitet på plattformen som kan styres eksternt. Den endelige FPGA-plattformen implementerer en dynamisk rekonfigurering styrt eksternt, med to forskjellige maskinvare konfigurasjoner. Resultatet av en aritmetisk operasjon er vist i et webservet grensesnitt, der en kan velge å laste ned en adderende maskinvarekonfigurasjon, og en subtraherende maskinvarekonfigurasjon. Resultatet av operasjonen er da selvfølgelig avhengig av hvilken maskinvarekonstruksjon som er lastet ned til FPGAen. En del av dokumentasjonen i rapporten er direkte skrevet for eventuelt videre arbeid med akkurat denne utviklingsplattform og de designverktøy som er brukt. Det er gitt forslag til hva det kan være lurt å jobbe videre med, og hvilke oppgaver som må prioriteres for å komme nærmere et ferdig AHEAD system. Til slutt er det gitt en konklusjon av arbeidet og hvordan fremdriften har vært.