<p>This thesis is divided into two parts, the design of a practical first order open loop sigma-delta modu- lator using discrete components, and simulation of a third order OLSD ADC to investigate the consequences of circuit imperfections - and determining circuit requirements if the ADC should be used in a GSM system. The practical modulator is designed as a first order OLSD ADC, with standard discrete components such as operational amplifiers and switches, and a microcontroller with a built in ADC. The practical circuit uses surface mount capacitors with a tolerance of 20%, resulting in poor matching and inaccurate behavior of the modulo integrator. Despite the poor matching, the OLSD ADC shows a distinct noise shaping, with a slope of about 20dB per decade. The quantization noise is not the dominating noise source in the circuit, and the quantizer resolution must to be set to four bits or less to achieve any improvement in performance over the standard ADC. The third order modulator is modeled and simulated at a behavior level using VHDL-AMS. The ideal circuit confirms the results from the preliminary project [12], where the quantizer resolution had to be equal to or larger than the modulator order to obtain proper noise shaping. The simulations shows that the ideal third order modulator with a four bit quantizer can achieve a SNR of 88:51dB, and an ENOB of 13:78bits within a 200kHz band. The third order modulator is simulated with circuit imperfections to determine the effect of these when there is no feedback present. Introducing finite gain in the integrators results in harmonic distortion at the output. This harmonic distortion is a result of leakage of the internal reset signal in the integrators. By setting the gain in all three integrators to 2OSR = 42dB, the SNR of the third order modulator sinks to 71:74dB. The gain in the ¯rst integrator is increased to 60dB, and the SNR raises to 84:52dB. The first integrator is the most crucial to the performance of the modulator, as is the case for conventional sigma-delta ADCs. The circuit is also simulated with capacitance mismatch and comparator o®set in the modulo integrator. These two imperfections results in the same error - the output voltage from the integrator di®ers from the ideal case. Simulations show that the total voltage error should be significantly less than 0.5VLSB to obtain the noise shaping. If the integrator output error is too large, the noise shaping will totally disappear. In general, it has been proved that the OLSD modulator with modulo integrators works as intended, the quantization noise is shaped like in conventional sigma-delta modulators. The modulator is very sensitive to capacitor mismatch and parasitics. The e®ect of these capacitor imperfections will increase as the quantizer resolution increase, because the error will cover more units of VLSB. It is important to minimize these capacitor effects, as increased quantizer resolution will allow a greater input signal swing.</p>

<p>This master thesis presents the design of a high IIP2 direct-conversion receiver front-end, consisting of a LNA and I- and Q-channel mixers. The front-end is implemented in a 0.18 μm technology with 1.8V supply voltage. Problems that are especially severe for direct-conversion receivers are presented; 1/f-noise, DC offset, and second-order nonlinearity, with particular attention to the latter. Methods to improve the IIP2 are presented and explored in the design of the front-end. The complete front-end has -19.7 dBm IIP3, 4 dB noise figure, and consume 7.4mA of current from a 1.8V supply. Through mixer load tuning an IIP2 of more than +48 dBm is achieved for the front-end.</p>

<p>Two different processors from two FPGA vendors and an OpenCore-processor have been investigated. For this work two different boards were used, the first was the Cyclone II FPGA Altera Board, in which the Nios II Altera microprocessor and the free processor Leon2 were tested. The second board was a SUZAKU-S board, in which the Microblaze Xilinx microprocessor and the free processor Leon2 were tested. We performed two different benchmarks in these boards, the Dhrystone and the Whetstone, to compare the different velocities between the free and not free processors. Also the documentation and ease of use of the processors is considered.</p>

<p>The Lithium-ion battery is today used by close to every portable battery powered device, and this marked is constantly increasing because not only are the products the consumer have had for years getting more and more sophisticated, so he or she often “has” to replace yesterdays model with tomorrows. But as many products are furnished with new functions they use more power, hence their battery life is shortened. Because the Lithium-ion battery is so chemically advanced, it requires a sophisticated management system if it is to be fully utilized by the product. In this report, the parameters of the Lithium-ion battery which are the reason for this strict management are explained. The explanation does not look into the underlying chemistry for them because that is beyond the scope of this report. But sources for further reading on the subject are included. Different solutions for battery management are discussed and a Voltage-to-Frequency (VFC) converter is implemented in VHDL-AMS and simulated in ADVance-MS from Mentor[2]. The sources of error in the design are identified but dealt with in this report. This is not necessary before implementation in a CMOS-process has been shown possible. Simulations without component deviations are good, but once they are introduced, the converter shows that it is too sensitive for them. This can be solved utilizing digital error correction and calibration. After the ideal simulations are performed, transistor level simulations for the circuit are performed. Different solutions and requirements for the various components in the Voltage-to-Frequency converter are looked into with respect to the results found while simulating the ideal circuit. It was found that the comparator should have hysteresis to avoid unwanted chattering in its output signal. The architecture was chosen and the comparator was simulated. It was found that this architecture provided some offset-voltage, but this can easily be compensated by subtracting the offset from its reference voltage. Digital calibration can also here be utilized, but this is not looked into. Two high-gain op-amp architectures are looked into and simulated in this report, it was found that the two-stage used slightly more power than the two-stage op-amp with cascode-output, but they both provided approximately the same gain, even though the two-stage op-amp with cascode-output theoretically should provide about 100 times more gain. From this it is concluded that this architecture has a gain-limit independent of architecture used around 56dB. It is concluded that the Voltage-to-Frequency-architecture looked into is not suitable for implementation in this CMOS-process and that another architecture must be found if a Voltage-to-Frequency converter shall be made for the architecture.</p>

<p>This Master’s thesis documents a new test method for detection of small delay faults in FPGA routing network. The main purpose of the test is accurate detection of faults in all parts of the network. The second aim is minimizing test application time. The work of the thesis consisted of four parts. First, a literature study was performed to get background knowledge of FPGA architecture and basics of testing. Second, detection accuracy was defined and measured in SPICE for test paths with different number of fan-out. Third, test configurations were developed. And finally, detection accuracies for the proposed test method were calculated. The SPICE measurements were performed on an interconnect model of FPGA. They revealed that detection accuracy of defects tested by branches of a test path is less than detection accuracy of defects tested by stems of a test path. In addition, it was observed that detection accuracy is best in the beginning of a test path. In the proposed test method detection accuracy is improved by testing all segments outside switch matrices by test path stems, and applying test patterns to all bidirectional segments in both directions. A comparison to two previous test methods showed that the proposed test method is more accurate while keeping the same number of test configurations. The detection accuracy can be improved further by allowing more test configurations.</p>

<p>When new transistor technology is used in a microcontroller design, the transistors become smaller. They cannot withstand the same voltages as older technology, because of their size. The automotive industry still uses 5V as a standard voltage, and the automotive industry is a major costumer for microcontroller companies. The microcontroller must therefore be able to use5V. This must be done without the need of external voltage regulator. To still be a supplier to the automotive industry, the AVR needs to be able to withstand voltages up to 5.5V. The main problem with the new transistor technology is the leakage currents. Traditionally, the CMOS devices have used power only when during switching of logical levels. This is no longer true, since the leakage currents have become so large. When using new transistor technology, the dynamic power usage will be reduced, but the total power usage will be increased, if nothing is done to prevent it. One solution to this is to make a multiple power domain microcontroller. The idea is that one power domain can withstand voltages up to 5.5V. The microcontroller then uses an internal voltage regulator to scale down the voltage to a suitable level. The low voltage area will then have a suitable voltage level, which reduces both the dynamic- and leakage power usage. The different voltage domains uses different clock sources, so communicating between them requires both level shifters to deal with the different voltage levels, and synchronization logic to prevent metastability. This assignment uses two voltage domains, VIO and VCORE. Since voltage regulators are quite inefficient, it is most efficient to use only two domains. The VCORE domain contains most of the digital logic of the microcontroller, such as the CPU, SRAM and timers. This domain uses a high-speed clock source, and a VCORE data bus to communicate between each other. To communicate with the VIO domain, the data bus is connected to the VIO data bus through an asynchronous communication scheme block. This is because the VIO domain uses a low speed clock source. The usage of individual clock sources prevents clock skew problems that may occur when passing level shifters, and there is power saving by using only a low speed clock source on the VIO domain. The VIO domain contains the Power Management Unit (PMU). The PMU shall control the power usage of the microcontroller. During active mode, the PMU can set unused modules in sleep mode, or shut them completely off. Most of the power savings are during sleep mode though. This is because a microcontroller such as the AVR spends most of the time in sleep mode. To reduce the power usage in sleep mode, the leakage currents needs to be reduced. The best way of doing so is to disconnect the power from the circuits. If the voltage regulator is disconnected, and all the inputs are set to high impedance, the VCORE domain is completely disconnected from the power, and uses absolutely no power. An asynchronous wake up circuit is designed to make it possible to wake up the microcontroller from a sleep mode without the usage of synchronized digital logic. Then the low frequency oscillator can be turned off, and even more power is saved. The major disadvantage of the multiple power domain solution is the start up time from a sleep mode. If the power to the low voltage area is disconnected, the start up requires that all the capacitors become charged before the chip can start running again. The oscillator is shut off, and it takes time to stabilize the oscillator. Especially since the oscillator requires some stability in the voltage, and the voltage may not stable until the capacitors are charged. Simulations shows that the multiple power domain solution has great potential of power saving. The proposed asynchronous wake up circuit uses only 1.2275nA. This is significantly smaller than the AVR uses in the deepest sleep mode today. To get a secure microcontroller, a reset circuit has to be on to be able to reset the AVR if necessary. The power usage of the reset circuit used today is confidential Atmel information, and cannot be published in this assignment. By looking at the data sheet of a pico power circuit of the AVR, the ATmega329p, one can see that in the deepest sleep mode, the microcontroller uses 40nA at 1.8V. By assuming that the reset circuit does not use more that half of this current, the total amount of power that saved during a sleep mode by using the multiple power domain solution is about 47%.</p>

<p>Wireless data networks have seen rapid growth and deployment in the recent years, replacing traditional wired data networks. WesternGeco is currently using a traditional wired data network in the land seismic operations to connect the Head Vibrator with the Recording Truck. The thesis provides a survey of the most important wireless data network technologies available. A comparison between them is done in order to determine the best suited for WesternGeco’s communication mechanism. The study has lead to the conclusion that IEEE 802.11g is the most suited technology. Through the use of high gain antennas, modification of MAC layer parameters and the proper channel allocation, the suggested solution is capable of responding what WesternGeco needs.</p>

<p>Today Lithium Ion batteries are extensively used in all kinds of electronic equipment due to its superior properties. However, Lithium Ion batteries need to have all the individual cells monitored to ensure the safety and long life time. This master thesis' objective is to design a managing system for a ten cell Lithium Ion battery with an Atmel AVR microcontroller. The main challenge was to scale down the high voltage level a 10 cell battery has and still maintain accuracy when reading this voltage with the AVR. This was solved by using current sense monitors which can handle large common mode voltages. Hardware was made to show proof of concept. It was found that the scaling circuitry had an accuracy of 46mV. In competition with other single chip devices, some other methods have to be found. The design in this thesis is physically too large and too expensive to be of any commercial use. However some other methods worth looking into have been proposed in the last chapter.</p>

<p>High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power. In this thesis, some research is done in how to optimize a software and hardware development for ultra low power consumption. A cardiac beat detector algorithm is implemented in ANSI C, and optimized for low power consumption, by using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies. This processor is optimized further for ultra low power consumption by applying application specific hardware, and by using several hardware power optimization techniques. A general processor and the optimized processor has been mapped on a chip, using a 90 nm low power TSMC process. Information about power dissipation is extracted through netlist simulation, and the results of both processors have been compared. The optimized processor consume 55% less average power, and the duty cycle of the processor, i.e., the time in which the processor executes its task with respect to the time budget available, has been reduced from 14% to 2.8%. The reduction in the total execution cycle count is 81%. The possibilities of applying power gating, or voltage and frequency scaling are discussed, and it is concluded that further reduction in power consumption is possible by applying these power optimization techniques. For a given case, the average leakage power dissipation is estimated to be reduced by 97.2%.</p>

<p>Digital multipliers are an important part of most of digital computation systems, such as microcontrollers and microprocessors. Multiplication operation is a quite complex task, thus there is many different solution varying in area, speed and power consumption. An important notice is that multipliers often are a part of critical path of a system which makes them especially important for these factors. During last decade, power efficiency has become an important issue in digital design and a lot of design methods has been created and investigated to meet this subject. It is a known fact that most of power consumed by arithmetic circuit is dissipated by hazards and toggles (up to 75%), that do not bring any information to final result. The method of evaluating the amount of spurious switching and its effect on power dissipation is investigated here. This thesis aims to find a method to estimate switching characteristics and its effect on power dissipation of eight supplied multipliers given in form of HDL net-list with some software overhead. As switching generally stands for majority of power consumption in digital CMOS circuits, this effect gives also good indication of overall power dissipation. One of the difficulties in estimating average power and transition density is pattern dependency problem. The method based on Monte Carlo technique is used where an adequate accuracy is obtained within moderate time and resource usage. Three of investigated multipliers are net-lists created by using methodology developed in [21]. These are synthesized and laid out in the technology used by Atmel Norway. The amount of logical state changes is compared from pre- and post- synthesis net-lists. The technology mapped net-lists are also examined for power consumption to see the connection between switching and dynamic power dissipation. The fan-out delay model used to estimate total toggling gives a good approximation of circuit properties; it is however too simple to give a good estimate of spurious toggling inside the circuit and its effect on power consumption. The same estimation technique is used to investigate a DesignWare circuit (DW02) which is an industrial approach of building fast and power efficient multipliers. The results show that this is the most power effective solution among the examined circuits (45-47% less than the most power efficient circuit from [21]) It is also a solution with smallest amount of hazards during a multiplication operation (38-52%). A circuit generated by module generation software (ModGen) is also investigated. This solution is quite power efficient, it has however largest amount of power dissipated by the spurious toggling (62-68%). It is also noticed that transition density and what follows the power dissipation in strongly dependent on the process, temperature and voltage variation. In fact the higher temperature gives reduction in power consumption.</p>