Today’s thin-film passive components such as capacitors and inductors are limited to low volumetric density and large form-factors that pose as major roadblock to miniaturization of the power modules. These components are also placed far away from the IC’s leading to large interconnect parasitics and lower operating frequencies. Novel thin-film technologies with high densities and small form-factors are, therefore, required to enable miniaturization and performance at high frequencies. Glass- and silicon- based interposer technologies that utilize vertical through-via interconnections have shown way to improve power distribution network (PDN) performance with thin power-ground planes. However, integration of ultra-high density capacitors in such substrates has not yet been demonstrated. This thesis addresses these challenges with tantalum-based, silicon-integrated, ultrathin, high-density capacitors at higher operating frequencies with lower leakage properties (<0.01µA/µF). The anodization kinetics of tantalum pentoxide and the underlying leakage current mechanisms are investigated to provide optimal process guidelines. The thin-film Ta capacitors demonstrated capacitance density of 0.1 µF/mm2 at 1-10 MHz in form-factors of 50 µm, which corresponds to 6X higher volumetric density relative to commercial tantalum capacitors. An innovative approach to address incompatibility of tantalum electrodes with substrates is pursued by prefabricating the electrodes on a free-standing foil, which are then transferred onto the active wafer to form the capacitors on Si. The integration approach is designed to embed these thin tantalum capacitors on alternative substrates such as organic, glass or silicon, with copper via interconnections for lower parasitics. The thesis also explores titanium-based high-density capacitors with high-permittivity titania dielectric as a potential alternate high-density capacitor technology.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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This project is a site specific based exploration into the boundaries between the domestic home and the navigation of the anxious corporeal body which dwells in the space. These connections open up ways of mapping anxiety brought on through intrusive thoughts surrounding contamination (in relation to Obsessive Compulsive Disorder). The corporal navigation of the domestic is fuelled by the thoughts and their control over the notions of fear and anxiety surrounding the transferring of contaminated material from the external temporal world (dust and organic matter) into the internal sterile environment through movement or fissures in the fabric of the dwelling. The project explores the notions of the domestic space being formed into a container for the intrusive thoughts through physical acts of decontaminating, containment, sealing and expelling the elements of dirt; the body and the home become a hybrid entity alluding to the extreme control which forms and takes over the domestic space.

<p>Osseointegrated titanium implants have become a commonly used method in edentulous jaws and today there are success rates in the magnitude of 82 % in the lower jaw and 98 % in the upper. During first year after implantation a fully normal marginal bone loss of 1-2 mm occurs. If the bone loss continues there is a risk of implant failure. High tensions in bone and inflammation caused by bacteria are possible reasons for this problem. It has been shown that a leakage of bacterias occurs between the parts of the implant and there are theories that this has effects on the marginal bone loss.</p><p>The aim of this thesis has been to increase the knowledge about microbial leakage with help of in vitro tests and virtual simulations. The goal was to create a test method to measure differences of microbial leakage in two implant systems.</p><p>The developed test method includes an in vitro test of six implants and Finite Element Analysis. The test method is the product of a process with several small tests. The final test method measures leakage of a coloured fluid with a spectrophotometer. The results are then compared with the virtual simulations to draw conclusions and find explanations how the implants are functioning.</p><p>The result of test on six implants, four Ospol and two Nobel Replace, indicates that there are differences in the magnitude of microleakage in different implant systems in due to the implant-abutment interface. No conclusions can be drawn before the test method is refined and more implants are tested.</p>

La evolución de los dispositivos MOS ha conllevado una reducción de tamaño de los mismos con el fin de mejorar sus prestaciones. Sin embargo, este continuo escalado se ha topado con un límite físico: la delgada capa aislante de SiO2 (entre otros), que fuerza la búsqueda de nuevas alternativas que permitan abastecer al exigente mercado tecnológico. En las dimensiones en las que actualmente se trabaja, del orden de nanómetros, los fenómenos cuánticos adquieren gran importancia siendo, entre otros, las corrientes de fuga uno de los principales escollos con los que se ha de lidiar. Estas corrientes provocan un aumento del consumo de potencia y disminución de la fiabilidad del dispositivo. Entre las alternativas que se perfilan como posibles opciones para reducir estas corrientes de fuga, la sustitución del hasta ahora principal aislante de la electrónica, el SiO2, por un material con una mayor constante dieléctrica, high-k (HK), ocupa una posición aventajada. Estos nuevos materiales HK permitirían mantener la misma capacidad del óxido que se obtendría usando un determinado grosor de SiO2 pero, utilizando un grosor físico mayor, reduciendo de esta manera las corrientes de fuga a través de la puerta del MOSFET. Aunque es una idea ampliamente aceptada no por ello es una tarea sencilla, ya que la introducción de estos nuevos materiales no está exenta de problemas que puedan influir en la fiabilidad del dispositivo. Por ejemplo, la morfología de los high-k y su impacto en las propiedades eléctricas del stack son factores importantes que deben ser considerados ya que pueden influir en el correcto funcionamiento del dispositivo. Los materiales bajo estudio son varios y diversos, pero gran parte de la comunidad científica apunta hacia el HfO2, o aleaciones relacionadas, y el Al2O3, como sustitutos del SiO2. Esta tesis, enmarcada en el campo de la microelectrónica, y concretamente en el estudio de la fiabilidad y caracterización eléctrica de los dispositivos MOS (Metal Óxido Semiconductor) de última generación, basados en HfO2, se centra principalmente en la evaluación, a escala nanométrica, de las propiedades morfológicas y eléctricas de dispositivos MOS fabricados con dieléctricos high-k (en concreto el HfO2). Particularmente, se analiza la influencia de la cristalización de la capa de HfO2, característica que adquiere tras haber sido sometida a un proceso de annealing durante el proceso de fabricación, en las propiedades eléctricas de la misma. Dicha cristalización puede alterar las propiedades morfológicas del material, lo que a su vez, puede repercutir en su homogeneidad eléctrica y su fiabilidad. También se ha llevado a cabo el estudio a escala nanométrica del fenómeno Resistive Switching, principal principio de operación de las memorias resistivas de acceso aleatorio (ReRAM). La evaluación del impacto de la cristalización, a escala nanométrica, se ha llevado a cabo mediante el uso de técnicas y herramientas de caracterización con resoluciones nanométricas como el AFM (Atomic Force Microscope) y técnicas relacionadas como el C-AFM (Conductive Atomic Force Microscope) o el Kelvin Probe Force Microscope (KPFM). / The evolution of MOS devices has involved an important shrinking in the transistor size with the aim of improve their benefits. However, this continuous miniaturization has found its physical limits in the thin SiO2 dielectric layer with current sizes at nanometric scale. Due to the continuous SiO2 layer thickness shrinking in a MOS transistor, tunnelling current increased more and more becoming the dominant source of device leakage. The main consequences of this leakage current enlargement are, on one hand, the consumption increase and, on the other hand, the impoverishment of the reliability of the device, which can be understood as an increment of the probability that the device failure happens for shorter times than usually. As a possible alternative to reduce the tunnelling current and also to avoid reliability issues, materials with higher dielectric constant were proposed to replace the SiO2 layer. These materials, known as high-k dielectrics, allow to obtain the equivalent performance for the capacitance with a larger physical thickness reducing, therefore, the leakage current. However, this substitution, although it sounds simple it is really a complicate issue since the introduction of new materials has associated new challenges and difficulties that must be solved. For example, the morphology of the high-k material and its impact on the electrical properties of the stack are important factors to be considered. Different materials are under study but HfO2, and related alloys, and Al2O3 are highlighted materials. This thesis, enshrined in the field of microelectronics and, specifically, in the reliability and electrical characterization of MOS devices based on high-k dielectrics, has been devoted to the analysis of nanoscale morphological and electrical properties of thin HfO2 layers with the aim to gain more insight in these new materials and related problems. Concretly, the influence of their polycrystallization on the electrical properties and breakdown (BD) of a HfO2 based gate stack has been evaluated. The study of the Resistive Random Access Memory (ReRAM) operating principle, Resistive Switching (RS), has been also investigated on MIM structures with HfO2 as dielectric. Since many of the problems associated to these materials (like, for example, their polycrystallization) and the failure mechanisms that affect the gate oxide are phenomena that have been found to have a nanometric origin, these analyses have been performed with AFM and related techniques as CAFM (Conductive Atomic Force Microscopy) or KPFM (Kelvin Probe Force Microscopy).

FPGAs have become quite popular for implementing digital circuits and systems because of reduced costs and fast design cycles. This has led to increased complexity of FPGAs, and with technology scaling, many new challenges have come up for the FPGA industry, leakage power being one of the key challenges. The current generation FPGAs are being implemented in 90nm technology, therefore, managing leakage power in deep-submicron FPGAs has become critical for the FPGA industry to remain competitive in the semiconductor market and to enter the mobile applications domain. <br /><br /> In this work an analytical state dependent leakage power model for FPGAs is developed, followed by dual-Vt based designs of the FPGA architecture for reducing leakage power. <br /><br /> The leakage power model computes subthreshold and gate leakage in FPGAs, since these are the two dominant components of total leakage power in the scaled nanometer technologies. The leakage power model takes into account the dependency of gate and subthreshold leakage on the state of the circuit inputs. The leakage power model has two main components, one which computes the probability of a state for a particular FPGA circuit element, and the other which computes the leakage of the FPGA circuit element for a given input using analytical equations. This FPGA power model is particularly important for rapidly analyzing various FPGA architectures across different technology nodes. <br /><br /> Dual-Vt based designs of the FPGA architecture are proposed, developed, and evaluated, for reducing the leakage power using a CAD framework. The logic and the routing resources of the FPGA are considered for dual-Vt assignment. The number of the logic elements that can be assigned high-Vt in the <em>ideal</em> case by using a dual-Vt assignment algorithm in the CAD framework is estimated. Based upon this estimate two kinds of architectures are developed and evaluated, homogeneous and heterogeneous architectures. Results indicate that leakage power savings of up to 50% can be obtained from these architectures. The analytical state dependent leakage power model developed has been used for estimating the leakage power savings from the dual-Vt FPGA architectures. The CAD framework that has been developed can also be used for developing and evaluating different dual-Vt FPGA architectures, other than the ones proposed in this work.

CMOS technology is scaling down to meet the performance, production cost, and power requirements of the microelectronics industry. The increase in the transistor leakage current is one of the most important negative side effects of technology scaling. Leakage affects not only the standby and active power consumption, but also the circuit reliability, since it is strongly correlated to the process variations. Leakage current influences circuit performance differently depending on: operating conditions (e.g., standby, active, burn in test), circuit family (e.g., logic or memory), and environmental conditions (e.g., temperature, supply voltage). Until the introduction of high-K gate dielectrics in the lower nanometer technology nodes, gate leakage will remain the dominant leakage component after subthreshold leakage. Since the way designers control subthreshold and gate leakage can change from one technology to another, it is crucial for them to be aware of the impact of the total leakage on the operation of circuits and the techniques that mitigate it. Consequently, techniques that reduce total leakage in circuits operating in the active mode at different temperature conditions are examined. Also, the implications of technology scaling on the choice of techniques to mitigate total leakage are investigated. This work resulted in guidelines for the design of low-leakage circuits in nanometer technologies. Logic gates in the 65nm, 45nm, and 32nm nodes are simulated and analyzed. The techniques that are adopted for comparison in this work affect both gate and subthreshold leakage, namely, stack forcing, pin reordering, reverse body biasing, and high threshold voltage transistors. Aside from leakage, our analysis also highlights the impact of these techniques on the circuit's performance and noise margins. The reverse body biasing scheme tends to be less effective as the technology scales since this scheme increases the band to band tunneling current. Employing high threshold voltage transistors seems to be one of the most effective techniques for reducing leakage with minor performance degradation. Pin reordering and natural stacks are techniques that do not affect the performance of the device, yet they reduce leakage. However, it is demonstrated that they are not as effective in all types of logic since the input values might switch only between the highly leaky states. Therefore, depending on the design requirements of the circuit, a combination, or hybrid of techniques which can result in better performance and leakage savings, is chosen. Power sensitive technology mapping tools can use the guidelines found as a result of the research in the low power design flow to meet the required maximum leakage current in a circuit. These guidelines are presented in general terms so that they can be adopted for any application and process technology.

As VLSI technology scales, the enhanced performance of smaller transistors comes at the expense of increased power consumption. In addition to the dynamic power consumed by the circuits there is a tremendous increase in the leakage power consumption which is further exacerbated by the increasing operating temperatures. The total power consumption of modern processors is distributed between the processor core, memory and interconnects. In this research two novel power management techniques are presented targeting the functional units and the global interconnects. First, since most leakage control schemes for processor functional units are based on circuit level techniques, such schemes inherently lack information about the operational profile of higher-level components of the system. This is a barrier to the pivotal task of predicting standby time. Without this prediction, it is extremely difficult to assess the value of any leakage control scheme. Consequently, a methodology that can predict the standby time is highly beneficial in bridging the gap between the information available at the application level and the circuit implementations. In this work, a novel Dynamic Sleep Signal Generator (DSSG) is presented. It utilizes the usage traces extracted from cycle accurate simulations of benchmark programs to predict the long standby periods associated with the various functional units. The DSSG bases its decisions on the current and previous standby state of the functional units to accurately predict the length of the next standby period. The DSSG presents an alternative to Static Sleep Signal Generation (SSSG) based on static counters that trigger the generation of the sleep signal when the functional units idle for a prespecified number of cycles. The test results of the DSSG are obtained by the use of a modified RISC superscalar processor, implemented by SimpleScalar, the most widely accepted open source vehicle for architectural analysis. In addition, the results are further verified by a Simultaneous Multithreading simulator implemented by SMTSIM. Leakage saving results shows an increase of up to 146% in leakage savings using the DSSG versus the SSSG, with an accuracy of 60-80% for predicting long standby periods. Second, chip designers in their effort to achieve timing closure, have focused on achieving the lowest possible interconnect delay through buffer insertion and routing techniques. This approach, though, taxes the power budget of modern ICs, especially those intended for wireless applications. Also, in order to achieve more functionality, die sizes are constantly increasing. This trend is leading to an increase in the average global interconnect length which, in turn, requires more buffers to achieve timing closure. Unconstrained buffering is bound to adversely affect the overall chip performance, if the power consumption is added as a major performance metric. In fact, the number of global interconnect buffers is expected to reach hundreds of thousands to achieve an appropriate timing closure. To mitigate the impact of the power consumed by the interconnect buffers, a power-efficient multi-pin routing technique is proposed in this research. The problem is based on a graph representation of the routing possibilities, including buffer insertion and identifying the least power path between the interconnect source and set of sinks. The novel multi-pin routing technique is tested by applying it to the ISPD and IBM benchmarks to verify the accuracy, complexity, and solution quality. Results obtained indicate that an average power savings as high as 32% for the 130-nm technology is achieved with no impact on the maximum chip frequency.