Les oscillateurs sont des blocs qui figurent dans presque tous les circuits. En effet,ils sont utilisés pour générer les signaux de synchronisation (les horloges), les signauxmodulés et démodulés ou récupérer des signaux noyés dans du bruit (détection synchrone).Les caractéristiques de ces oscillateurs dépendent de l'application. Dans le cas des boucles àverrouillage de phase (PLL), il existe de fortes exigences en matière de stabilité et de bruitde phase. En outre, face aux avancées des technologies nanométriques, il est égalementnécessaire de prendre en compte les effets liés à la variabilité des procédés de fabrication.Aujourd'hui, de nombreuses études sont menées sur les oscillateurs asynchrones en anneauqui présentent des caractéristiques bien adaptées à la gestion de la variabilité et qui offrentune structure appropriée pour limiter le bruit de phase. A ce titre, les anneaux asynchronessont considérés comme une solution prometteuse pour générer des horloges.Cette thèse étudie les avantages et les potentiels offerts par les oscillateursasynchrones en anneau. Deux applications principales ont été identifiées. D’une part, cesoscillateurs sont une solution prometteuse pour la génération d’horloges polyphasées àhaute fréquence et à faible bruit de phase. D’autre part, ils constituent une alternativesimple, dans une certaine mesure aux oscillateurs plus conventionnels et aux DLLs, car ilssont programmables en fréquence numériquement et sont susceptibles de fournir lesfonctionnalités d’arrêt de type gated clock de façon native. Plusieurs oscillateurs ont étéconçus, implémentés, fabriqués en technologie CMOS 65 nm de STMicroelectronics et,finalement, caractérisés sous pointes. Ces travaux ont notamment permis de démontrer lapertinence de ces oscillateurs, qui constituent une alternative sérieuse aux très classiquesoscillateurs en anneau à base d’inverseurs. / Oscillators are essential building blocks in many applications. For instance, they arebasic blocks in almost all designs: they are part of PLLs, clock recovery systems andfrequency synthesizers. The design of a low phase-noise multi-phase clock circuitry isespecially crucial when a large number of phases is required. There are plenty of workscovering the design of multiphase clocks. High frequency oscillators can be implementedusing ring structures, relaxation circuits or LC circuits. Ring architectures can easily providemultiple clocks with a small die size. With the advanced nanometric technologies, it is alsorequired to deal with the process variability, stability and phase noise. Today many studiesare oriented to Self-Timed Ring (STR) oscillators which present well-suited characteristicsfor managing process variability and offering an appropriate structure to limit the phasenoise. Therefore, self-timed rings are considered as promising solution for generatingclocks.This thesis studies the benefits and potential offered by Self-Timed Ring oscillators.Two main applications have been identified. On the one hand, these oscillators are apromising solution for the generation of high-frequency multi-phase low phase noise clocks.On the other hand, they are a simple alternative to some extent to the conventionaloscillators and DLLs, because they are digitally programmable. Several oscillators havebeen designed, implemented, manufactured in 65 nm CMOS technology fromSTMicroelectronics, and characterized. This work has demonstrated the relevance of theseoscillators, which are a serious alternative to the conventional ring oscillators based oninverters.

In this thesis, a low phase noise local oscillator operating at 2210 MHz is designed and implemented to be used in X-Band transmitter of a LEO satellite. Designed local oscillator is a PLL (Phase Locked Loop) based frequency synthesizer which is implemented using discrete commercial components including ultra low noise voltage controlled oscillator and high resolution, low noise fractional-N synthesizer. Operational settings of the synthesizer are done using three wire serial interface of a microcontroller. Although there are some imperfections in the implementation, phase noise of the prototype system is pretty good which is measured as -123.2 dBc/Hz at 100 kHz offset and less than -141.3 dBc/Hz at 1 MHz offset. Made up of discrete components, the VCO used in the designed local oscillator is not integrable to frequency synthesizer which is implemented in CMOS technology. Considering technological progress, integrabilitiy of system components becomes important for designing single chip complete systems like transmitters, receivers or transceivers. Therefore considering a potential single chip transceiver production, also a CMOS voltage controlled oscillator is designed using standard TSMC 0.18um technology operating in between 2.05 GHz and 2.35 GHz . Since low phase noise is the main concern, phase noise models and phase noise reduction techniques that are derived from the models are studied. These techniques are applied to the VCO core to see the effects. Design is finalized by applying some of those techniques which are found to be noticeably effective to the core design. Finalized core operates from 2.15 GHz to 2.25 GHz and phase noise is simulated as -107.265 dBc/Hz at 100 kHz offset and -131.167 dBc/Hz at 1 MHz offset. Also oscillator has figure of merit of -185.4 at 100 kHz offset. These values show that designed core is considerably good when compared to similar designs.

No description available.

Le but de cette thèse est la synthèse optique d'ondes millimétriques et submillimétriques avec un très bas bruit de phase. La première partie concerne la réalisation d'un laser biaxe bifréquence dont chacune des deux fréquences est accordable indépendamment et continûment sur 1 THz. Ce laser est caractérisé en bruit d'amplitude et de phase. Nous avons mis en évidence un facteur de couplage entre les fluctuations de puissance de la diode de pompe et le bruit de phase du laser. La deuxième partie concerne le développement d'un système amplificateur qui se compose d'un amplificateur EDFA et d'un SOA par polarisation. Ce système amplificateur permet d'obtenir une puissance de l'ordre de 17 dBm, tout en réduisant le bruit relatif d'intensité (RIN) d'une vingtaine de dB sur 1 GHz. Cet amplificateur est également un actionneur pour la stabilisation de puissance permettant un RIN de l'ordre de -150 dB/Hz de 3 Hz à 5 kHz. La dernière partie concerne la mise en place du banc cavité et de l'asservissement des fréquences du laser sur une cavité ultra-stable. Nous obtenons un bruit de phase, à 10 kHz pour une porteuse à 10 GHz, meilleur que le plancher de bruit d'un analyseur de bruit de phase hautes performances de l'ordre de -115 dBc/ Hz. Le bruit de phase du système est indépendant de la fréquence de battement. / The aim of this thesis is the optical synthesis of millimeter and submillimeter waves with a very low phase noise. The first part concerns the development of a dual-axis dual frequency laser, whose the two frequencies are tuneable independently and continuously on 1 THz. This laser is characterized in amplitude noise and phase noise. We have identified a coupling factor between the diode pump and the power fluctuations of the laser phase noise. In the second part, we report the development of an amplifier system which consists of an EDFA and a SOA per polarisation axis. This amplifier system delivers 17 dBm of power and reduces the relative intensity noise (RIN) by 20 dB on a 1 GHz bandwidth. This amplifier is also an actuator for the power stabilization to a RIN of the order of -150 dB/Hz from 3 Hz to 5 kHz. The last part concerns the setup of the cavity bench and the stabilization of the laser frequency on a ultrastable cavity. We obtain a phase noise at 10 kHz of frequency offset on a 10 GHz carrier better than the noise floor of a phase noise analyser with high performance of the order of -115 dBc/Hz. The system phase noise is independent of the beatnote frequency.

No description available.

K-Band (18 to 26 GHz) dielectric resonator oscillators are typically used as a local oscillator in most K-Band digital transmitter/receiver topologies. Traditionally, the oscillator itself is made up of an active device, a dielectric resonator termination network, and a passive load matching network. The termination network embodies a cylindrical high permittivity dielectric resonator that is coupled on the same plane as a current carrying transmission line. This configuration provides an adequate resonance needed for oscillation but has some limitations. In order to provide a high Q resonance the entire oscillator is placed in a metal box to prevent radiation losses. This increases the overall size of the device and makes it difficult to integrate in smaller transceiver topologies. Secondly, a tuning screw is required to help excite the dominant mode of the resonator to achieve the high Q response. This can cause problems in precision due to the mechanical jitter of the screw inherent in mobile devices. By embedding this resonator inside the substrate it is possible to realize a very high Q resonance at a desired frequency and remove the need for a metal cavity and tuning screw. An additional advantage can be seen in terms of overall size reduction of the oscillator circuit. To demonstrate the feasibility of utilizing a dielectric resonator embedded within a substrate, a K-Band oscillator proof of concept has been designed, fabricated, and tested. The oscillator is comprised of a low noise active transistor device, an embedded k-band dielectric resonator and a passive transmission line load network. All elements within the oscillator are optimized to produce a steady oscillation near 20 GHz. Preliminary investigations of a microstrip resonator S-band (2-3 GHz) oscillator are first discussed. Secondly, various challenges in design and fabrication are discussed. Thereafter, simulated and measured results of the embedded DRO structure are presented. Emphasis is placed on output oscillation power and low phase noise. With further development, the entire oscillator can be embedded within the substrate leaving only the active device on the surface. This allows for a considerable reduction in material cost and simple integration with miniaturized digital transmitter/receiver devices.

No description available.

Following the rise of Internet of Things (IoT), or just the technological advancements and expectations in a world where the things are or will be connected, new demands are put on Integrated Circuit (IC) for wireless connectivity. The use cases seem endless; smart home, healthcare, entertainment, and science are all areas that can benefit from connectivity of low power electronics. But there are obstacles to overcome. Meeting the specifications, especially the phase noise requirements of modern high-speed wireless standards can be a challenge for devices that run on low supply voltages and are allowed only very limited power consumption. The focus of this thesis is the exploration of modern LC-oscillator architectures for RF-transceivers, and the design and post-layout evaluation of a Digitally Controlled Oscillator (DCO) intended to be used in an All-Digital Phase Locked Loop (ADPLL) in a 22 nm FD-SOI process. The DCO specifications are set by an ADPLL for the Wi-Fi 6 (MCS 11) standard. The ADPLL is replacing the blocks that are usually implemented as noise-sensitive analog components with more robust digital blocks that are easier to integrate with baseband- and digital-circuitry. A dual-core class-C oscillator with a dynamic-biasing circuit is proposed and designed to meet the specification of -121 dBc/Hz phase noise at a 1 MHz offset from 7.8 GHz, a –7.18.6 GHz tuning range, and a frequency resolution of at most 35 kHz around 7.8 GHz. The phase noise specification is met; a phase noise of -121 dBc/Hz at the 1 MHz offset from 7.8 GHz is achieved in post-layout simulation along with a Figure of Merit (FoM) of 189.9, and an average tracking frequency step of 5.8 MHz. The tuning range specification was not met, but it is reasonable to believe that the specified range can be met after some redesign of the capacitor banks. Further work will be required. / Till följd av tillväxten inom Internet of Things (IoT), eller bara de teknologiska framgångar och förväntningar på en värld där dem flesta saker är eller kommer att bli uppkopplade, ställs nya krav på Integrated Circuit (IC)-komponenter för trådlös uppkoppling. Tillämningsområdena är oändliga; smart home, sjukvård och hälsa, underhållning och forskning är områden som som kan dra nytta av nya uppkopplingsmöjligheter med extremt strömsnål elektronik. Att leva upp till specifikationerna för moderna trådlösa höghastighetsuppkopplingar, speciellt när det kommer till fasbrus, kan dock vara en utmaning för enheter som måste klara sig med en väldigt begränsad effektåtgång. Fokus för denna avhandling är design och utvärdering på schematik och layout-nivå av en Digitally Controlled Oscillator (DCO) för en 22 nm Fully Depleted Silicon-On-Insulator (FD-SOI)-process avsedd att klara specifikationen satt av en given All-Digital Phase Locked Loop (ADPLL) för Wi-Fi 6 (MCS 11) standarden. En DCO och ADPLL ersätter block som tidigare tillämpats som analoga bruskänsliga komponenter med robustare digitala komponenter som är enklare att integrera med bas-band och digital logik-kretsar. En dubbelkärnig klass-C DCO med en dynamisk biaskrets föreslås för att nå kravet på fasbrus på maximalt -121 dBc/Hz mätt vid 1 MHz från en frekvens på 7.8 GHz, med ett frekvensomfång 7.1-8.6 GHz och en frekvensupplösning under 35 kHz. Fasbruset vid denna 1 MHz från 7.8 GHz uppmättes i simulering till -121 dBc/Hz, och en Figure of Merit (FoM) på 189.9 har uppnåtts, samt en genomsnittlig frekvensupplösning på 5.8 MHz nära 7.8 GHz. Designen klarar inte av att möta kraven på frekvensomfång, men det är sannolikt att en liknande design kan möta specifikationen efter ytterligare revision. Ytterligare arbete krävs.