Recently, there have been a great interest in the millimeter-wave (mmW) and terahertz (THz) bands due to the unique features they provide for various applications. For example, the mmW is not significantly affected by the atmospheric constraints and it can penetrate through clothing and other dielectric materials. Therefore, it is suitable for a vast range of imaging applications such as vision, safety, health, environmental studies, security and non-destructive testing. Millimeter-wave imaging systems have been conventionally used for high end applications implementing sophisticated and expensive technologies. Recent advancements in the silicon integrated and low loss material passive technologies have created a great opportunity to study the feasibility of low cost mmW imaging systems. However, there are several challenges to be addressed first. Examples are modeling of active and passive devices and their low performance, highly attenuated channel and poor signal to noise ratio in the mmW. The main objective of this thesis is to investigate and develop new technologies enabling cost-effective implementation of mmW and sub-mmW imaging systems. To achieve this goal, an integrated active Rotman lens architecture is proposed as an ultimate solution to combine the unique properties of a Rotman lens with the superiority of CMOS technology for fabrication of cost effective integrated mmW systems. However, due to the limited sensitivity of on-chip detectors in the mmW, a large number of high gain, wide-band and miniaturized mmW Low Noise Amplifiers (LNA) are required to implement the proposed integrated Rotman lens architecture. A unique solution presented in this thesis is the novel Band Pass Distributed Amplifier (BPDA) topology. In this new topology, by short circuiting the line terminations in a Conventional Distributed Amplifier (CDA), standing waves are created in its artificial transmission lines. Conventionally, standing waves are strongly avoided by carefully matching these lines to 50 ?? in order to prevent instability of the amplifier. This causes that a large portion of the signal be absorbed in these resistive terminations. In this thesis, it is shown that due to presence of highly lossy parasitics of CMOS transistor at the mmW the amplifier stability is inherently achieved. Moreover, by eliminating these lossy and noise terminations in the CDA, the amplifier gain is boosted and its noise figure is reduced. In addition, a considerable decrease in the number of elements enables low power realization of many amplifiers in a small chip area. Using the lumped element model of the transistor, the transfer function of a single stage BPDAs is derived and compared to its conventional counter part. A methodology to design a single stage BPDA to achieve all the design goals is presented. Using the presented design guidelines, amplifiers for different mmW frequencies have been designed, fabricated and tested. Using only 4 transistors, a 60 GHz amplifier is fabricated on a very small chip area of 0.105 mm2 by a low-cost 130 nm CMOS technology. A peak gain of 14.7 dB and a noise figure of 6 dB are measured for this fabricated amplifier. oreover, it is shown that by further circuit optimization, high gain amplification can be realized at frequencies above the cut-off frequency of the transistor. Simulations show 32 and 28 dB gain can be obtained by implementing only 6 transistors using this CMOS technology at 60 and 77 GHz. A 4-stage 85 GHz amplifier is also designed and fabricated and a measured gain of 10 dB at 82 GHz is achieved with a 3 dB bandwidth of 11 GHz from 80 to 91 GHz. A good agreement between the simulated and measured results verifies the accuracy of the design procedure. In addition, a multi-stage wide-band BPDA has been designed to show the ability of the proposed topology for design of wide band mmW amplifiers using the CMOS technology. Simulated gain of 20.5 dB with a considerable 3 dB bandwidth of 38 GHz from 30 to 68 GHz is achieved while the noise figure is less than 6 dB in the whole bandwidth. An amplifier figure of merit is defined in terms of gain, noise figure, chip area, band width and power consumption. The results are compared to those of the state of the art to demonstrate the advantages of the proposed circuit topology and presented design techniques. Finally, a Rotman lens is designed and optimized by choosing a very small Focal Lens Ratio (FL), and a high measured efficiency of greater than 30% is achieved while the lens dimensions are less than 6 mm. The lens is designed and implemented using a low cost Alumina substrate and conventional microstrip lines to ease its integration with the active parts of the system.

L'engouement récent pour l'Internet des Objets comme pour les communications satellites entraine des besoins forts en systèmes de communication radio-fréquence (RF) performants. Afin de répondre aux contraintes du marché de masse, ces systèmes doivent être toujours moins encombrants et permettre de maitriser leur consommation de puissance. Ils doivent également être capable d'adresser plusieurs standards de communications et d'ajuster leur performances aux besoins de leur environnement, toujours afin de réduire leur taille et leur consommation. Actuellement, beaucoup de travaux se concentrent sur le développement d'amplificateurs faible-bruits (LNA), le bloc le plus critique des récepteurs RF. L'objectif est donc de concevoir des récepteurs multi-mode et multi-standard. Pour cela, les LNA nécessitent des flots de conception capables de s'adapter aux différentes technologies et topologies afin de répondre à des cahiers des charges très diverses. Cette thèse a donc pour objectif le développement de méthodologies de conception simple et précise pour l'implémentation d'amplificateurs faible bruit.La première méthodologie présentée est dédiée à l'implémentation de LNA en technologie COTS pour des applications spatiales. Ce LNA présente une adaptation large-bande pour adresser plusieurs standards. Il a été conçu pour faire partie d'un récepteur RF dédié aux nano-satellites. Ce dernier a donc fait l'objet d'une étude préliminaire afin de déterminer le cahier des charges à partir des normes des standards visés.La seconde méthodologie est dédiée à l'implémentation de LNA en technologie CMOS pour n'importe quelle type d'applications. Cette méthodologie est d'abord présentée au travers de topologies simples, puis appliquée à un LNA sans inductances à forte linéarité. Cette méthodologie permet notamment de comparer les topologies mais également les technologies CMOS, même les plus avancées telle que la 28 nm FDSOI.Enfin le LNA sans inductances est rendu reconfigurable pour adresser plusieurs standards tout en gardant le dimensionnement optimum obtenu par la méthodologie présentée précédemment. En effet les tailles et polarisation de chaque transistor sont contrôlées numériquement afin d'adapter les performances du LNA à un standard donné. De plus, l'étude de filtres de type N-path combinés au LNA proposé permet d'étendre encore la linéarité du circuit / The recent enthusiasm for the Internet of Objects as well as for satellite communications leads to the need for high-performance radio-frequency (RF) communication systems. In order to meet the constraints of the mass market, these systems must be compact and be as low power as possible. Beside, they are expected to address multiple communication standards and to adjust their performance to the environment, still in order to reduce the size and the power consumption. Currently, many works focus on the development of low-noise amplifiers (LNA), the most critical block of RF receivers. To address this purpose, the goal is to design multi-mode and multi-standard receivers. Hence, LNAs require design flows that can adapt to the different technologies and topologies in order to meet any given set of specifications. This thesis aims at the development of simple and accurate design methodologies for the implementation of low-noise amplifiers.The first proposed methodology is dedicated to the implementation of a LNA in COTS technology for spatial applications. This LNA offers a broadband matching to address several standards. It is designed to be part of an RF receiver for nano-satellites. Thus, the latter is first studied in order to determine the specifications based on the standards of the targeted applications.The second methodology is dedicated to the implementation of LNAs in CMOS technology for any kind of applications. This methodology is first illustrated with basic topologies and then applied to an highly linear inductorless LNA. The design methodology also enables a fair comparison between the topologies and also CMOS technologies, even the most advanced ones such as the 28 nm FDSOI.Finally, reconfigurability is added to the inductorless LNA, to address several standards while retaining the optimum sizing given by the previously introduced methodology. Indeed, the size and polarization of each transistor are digitally controlled in order to adjust the LNA's performance to a given standard. Furthermore, the study of N-path filters combined with the proposed LNA is explored to improve the linearity of the circuit.

Compared to current single-standard radio solutions, multi-standard radio transceivers enable higher integration, backward compatibility and save power, area and cost. The primary bottleneck in their realization is the development of high-performance frequency-reconfigurable RF circuits. To that end, this research introduces several CMOS-integrated, transformer-based reconfigurable circuit techniques whose effectiveness is validated through measurements of designed transceiver front-end low-noise (LNA) and power amplifier (PA) prototypes. In the first part, the use of high figure-of-merit phase-change (PC) based RF switches in the reconfiguration of CMOS LNAs in the receiver front-end is proposed. The first reported demonstration of an integrated, PC-switch based, dual-band (3/5 GHz) reconfigurable CMOS LNA with transformer source degeneration and designed in a 0.13 μm process is presented. In the second part, a frequency-reconfigurable CMOS transformer combiner is introduced that can be reconfigured to have similar efficiencies at widely separated frequency bands. A 65-nm CMOS triple-band (2.5/3/3.5 GHz) PA employing the reconfigurable combiner was designed. In the final part of this work, the use of transformer coupled-resonators in mm-wave LNA designs for 28 GHz bands was investigated. To cover contiguous and/or widely-separated narrowband channels of the emerging 5G standards, a 65-nm CMOS 24.9-32.7 GHz wideband multi-mode LNA using one-port transformer coupled-resonators was designed. Finally, a 25.1-27.6 GHz tunable-narrowband digitally-calibrated merged LNA-vector modulator design employing transformer coupled-resonators is presented that proposes a compact, differential quadrature generation scheme for phased-array architectures.

<p> This thesis contributes to the computer-aided design (CAD) of spiral inductors and LC resonators with spiral inductors exploiting full-wave electromagnetic (EM) analysis.</p> <p> The spiral inductor is widely used in radio frequency integrated circuits (RF ICs), such as low noise amplifiers (LNA) and voltage controlled oscillators (VCO). The design of spiral inductors has a direct influence on the performance of these circuits. Recently proposed optimization methods for spiral inductors are usually based on circuit models, which are computationally efficient but inaccurate compared with full-wave electromagnetic (EM) simulations.</p> <p> For the first time, we develop an optimization technique for the design of spiral inductors and LC resonators exploiting both the computational efficiency of a (cheap) circuit model and the accuracy of a full-wave EM analysis, based on geometric programming (GP) and space mapping (SM). With the new technique, we can efficiently obtain EM-validated designs with considerable improvement over those obtained with traditional optimization methods.</p> / Thesis / Master of Applied Science (MASc)

Este trabalho apresenta o projeto de um bloco LNA-Misturador dentro de um mesmo circuito integrado para aplicações em um receptor Bluetooth 2;45GHz. Uma estratégia de projeto bem clara, concisa e com uma boa base física e matemática foi desenvolvida para auxiliar o processo de projeto de um bloco LNA-Misturador, composto por um LNA cascode em cascata com um misturador de chaveamento de corrente com entradas simples e degeneração indutiva nas fontes dos estágios de transcondutância. Esta estratégia foi adaptada de trabalhos apresentados na literatura. A estratégia de projeto proposta considera o compromisso entre ruído, linearidade, ganho, dissipação de potência, casamento de impedâncias e isolamento de portas, usando as dimensões dos dispositivos e condições de polarização como variáveis de projeto. Com base nesta estratégia se obteve um bloco LNA-Misturador que atinge algumas especificações propostas. Um bloco LNA-Misturador foi projetado e fabricado em uma tecnologia CMOS 0;35µm para validar a estratégia de projeto proposta. Além disso, para atingir os objetivos, durante o desenvolvimento deste trabalho foi dada atenção especial no projeto dos indutores. Foi projetado, fabricado e medido um chip de teste. Para tal fim foram aplicadas técnicas e estruturas de de-embedding nas medidas para conseguir resultados mais confiáveis. Os resultados experimentais obtidos para os indutores e os resultados preliminares do bloco LNA-Misturador s~ao satisfatórios de acordo com as especificações e os esperados das simulações. No entanto, os indutores integrados degradam significativamente o desempenho do bloco LNA-Misturador. Se forem usados processos de fabricação nos quais os indutores apresentem melhor desempenho, os resultados do bloco LNA-Misturador aplicando a estratégia de projeto desenvolvida neste trabalho podem ser melhorados. Finalmente, é importante ressaltar que a estratégia de projeto proposta neste trabalho já está sendo usada e adaptada em outros projetos com o propósito de melhorar os resultados obtidos, e conseguir auxiliar o processo de projeto deste tipo de blocos. / This work presents a fully integrated LNA-Mixer design for a Bluetooth receiver application at 2:45GHz. A concise design strategy with good physics and mathematics basis was developed to assist the design process of a LNA-Mixer block, formed by a cascode LNA in cascade to a single balanced current commutation Mixer with inductive degeneration. This strategy was adapted from literature and considers the trade-offs between noise, linearity, gain, power dissipation, impedance matching and ports isolation, using the device dimensions and bias conditions as design variables. Based on this strategy, the proposed LNA-Mixer design specifications were achieved. To validate the proposed design strategy, the LNA-Mixer were fabricated in a 0:35µm CMOS process. Furthermore, to achieve the specifications, during the development of this work a special attention to the RF CMOS inductors was given. A test chip was designed, fabricated and measured applying de-embedding structures to obtain more reliable results. The experimental results obtained for the inductors and the preliminary results for the LNA-Mixer are satisfactory compared to the specifications and as expected from simulations. However, the integrated inductors degrade the performance of the block significantly and if a manufacturing process in which the inductor has better performance is used, the resulting LNA-Mixer design applying the strategy developed in this work can be improved. Finally, it is important to highlight that the design strategy proposed in this work is already being used and adapted in other designs in order to improve the results, and to assist the design process of such blocks.

Este trabalho apresenta o projeto de um bloco LNA-Misturador dentro de um mesmo circuito integrado para aplicações em um receptor Bluetooth 2;45GHz. Uma estratégia de projeto bem clara, concisa e com uma boa base física e matemática foi desenvolvida para auxiliar o processo de projeto de um bloco LNA-Misturador, composto por um LNA cascode em cascata com um misturador de chaveamento de corrente com entradas simples e degeneração indutiva nas fontes dos estágios de transcondutância. Esta estratégia foi adaptada de trabalhos apresentados na literatura. A estratégia de projeto proposta considera o compromisso entre ruído, linearidade, ganho, dissipação de potência, casamento de impedâncias e isolamento de portas, usando as dimensões dos dispositivos e condições de polarização como variáveis de projeto. Com base nesta estratégia se obteve um bloco LNA-Misturador que atinge algumas especificações propostas. Um bloco LNA-Misturador foi projetado e fabricado em uma tecnologia CMOS 0;35µm para validar a estratégia de projeto proposta. Além disso, para atingir os objetivos, durante o desenvolvimento deste trabalho foi dada atenção especial no projeto dos indutores. Foi projetado, fabricado e medido um chip de teste. Para tal fim foram aplicadas técnicas e estruturas de de-embedding nas medidas para conseguir resultados mais confiáveis. Os resultados experimentais obtidos para os indutores e os resultados preliminares do bloco LNA-Misturador s~ao satisfatórios de acordo com as especificações e os esperados das simulações. No entanto, os indutores integrados degradam significativamente o desempenho do bloco LNA-Misturador. Se forem usados processos de fabricação nos quais os indutores apresentem melhor desempenho, os resultados do bloco LNA-Misturador aplicando a estratégia de projeto desenvolvida neste trabalho podem ser melhorados. Finalmente, é importante ressaltar que a estratégia de projeto proposta neste trabalho já está sendo usada e adaptada em outros projetos com o propósito de melhorar os resultados obtidos, e conseguir auxiliar o processo de projeto deste tipo de blocos. / This work presents a fully integrated LNA-Mixer design for a Bluetooth receiver application at 2:45GHz. A concise design strategy with good physics and mathematics basis was developed to assist the design process of a LNA-Mixer block, formed by a cascode LNA in cascade to a single balanced current commutation Mixer with inductive degeneration. This strategy was adapted from literature and considers the trade-offs between noise, linearity, gain, power dissipation, impedance matching and ports isolation, using the device dimensions and bias conditions as design variables. Based on this strategy, the proposed LNA-Mixer design specifications were achieved. To validate the proposed design strategy, the LNA-Mixer were fabricated in a 0:35µm CMOS process. Furthermore, to achieve the specifications, during the development of this work a special attention to the RF CMOS inductors was given. A test chip was designed, fabricated and measured applying de-embedding structures to obtain more reliable results. The experimental results obtained for the inductors and the preliminary results for the LNA-Mixer are satisfactory compared to the specifications and as expected from simulations. However, the integrated inductors degrade the performance of the block significantly and if a manufacturing process in which the inductor has better performance is used, the resulting LNA-Mixer design applying the strategy developed in this work can be improved. Finally, it is important to highlight that the design strategy proposed in this work is already being used and adapted in other designs in order to improve the results, and to assist the design process of such blocks.

No / 5th Generation mobile networks (5G) and mobile communications technologies beyond 2020 will need to be energy aware so as to support services that are likely to be intelligent and bandwidth hungry, as well as to support multi-mode operation (LTE, LTE+, HSDPA, 3G among others) in a HetNet environment. This imposes stringent design requirements on the RF transceiver, a key consumer of power in networks today. This chapter will investigate the key RF subsystems forming part of the 5G RF transceiver, where energy efficiency and full radio flexibility are at the forefront of system design. In particular, we target advanced designs on antenna systems, RF power amplifiers and the challenges facing cross-talk in MIMO architectures.

This thesis describes a unique approach of turning on and off transistor cores to reconfigure low-noise amplifiers. A small footprint single-pole, single-throw switch is optimized for low insertion loss and high isolation. A narrowband (non-switchable) LNA is developed as a basis of comparison for reconfigurable designs. The optimized switch is incorporated into different switchable transistor core architectures. These architectures are investigated to determine their ability to reconfigure amplifier performance. One switchable transistor core topology is integrated into a cascode LNA design. An in depth stability analysis employing the S-probe technique is used to help improve the reliability of the cascode design. In addition, a single-pole, double-throw transmit/receive switch, as well as a deserializer are developed to help support the LNA block in a reconfigurable phased-array radar system. This type of flexible radar design is very beneficial in challenging electromagnetic environments.

Recent research focuses on expanding the use of RF/Microwave circuits and systems to include multi-disciplinary applications. One example is the detection of the dielectric properties of chemicals and bio-chemicals at microwave frequencies, which is useful for pharmaceutical applications, food and drug safety, medical diagnosis and material characterization. Dielectric spectroscopy is also quite relevant to detect the frequency dispersive characteristics of materials over a wide frequency range for more accurate detection. In this dissertation, on-chip and on-board solutions for microwave chemical sensing are proposed. An example of an on-chip dielectric detection technique for chemical sensing is presented. An on-chip sensing capacitor, whose capacitance changes when exposed to material under test (MUT), is a part of an LC voltage-controlled oscillator (VCO). The VCO is embedded inside a frequency synthesizer to convert the change in the free runing frequency frequency of the VCO into a change of its input voltage. The system is implemented using 90 nm CMOS technology and the permittivities of MUTs are evaluated using a unique detection procedure in the 7-9 GHz frequency range with an accuracy of 3.7% in an area of 2.5 × 2.5 mm^2 with a power consumption of 16.5 mW. The system is also used for binary mixture detection with a fractional volume accuracy of 1-2%. An on-board miniaturized dielectric spectroscopy system for permittivity detec- tion is also presented. The sensor is based on the detection of the phase difference be- tween the input and output signals of cascaded broadband True-Time-Delay (TTD) cells. The sensing capacitor exposed to MUTs is a part of the TTD cell. The change of the permittivity results in a change of the phase of the microwave signal passing through the TTD cell. The system is fabricated on Rogers Duroid substrates with a total area of 8 × 7.2 cm2. The permittivities of MUTs are detected in the 1-8 GHz frequency range with a detection accuracy of 2%. Also, the sensor is used to extract the fractional volumes of mixtures with accuracy down to 1%. Additionally, multi-band and multi-standard communication systems motivate the trend to develop broadband front-ends covering all the standards for low cost and reduced chip area. Broadband amplifiers are key building blocks in wideband front-ends. A broadband resistive feedback low-noise amplifier (LNA) is presented using a composite cross-coupled CMOS pair for a higher gain and reduced noise figure. The LNA is implemented using 90 nm CMOS technology consuming 18 mW in an area of 0.06 mm2. The LNA shows a gain of 21 dB in the 2-2300 MHz frequency range, a minimum noise figure of 1.4 dB with an IIP3 of -1.5 dBm. Also, a four-stage distributed amplifier is presented providing bandwidth extension with 1-dB flat gain response up to 16 GHz. The flat extended bandwidth is provided using coupled inductors in the gate line with series peaking inductors in the cascode gain stages. The amplifier is fabricated using 180 nm CMOS technology in an area of 1.19 mm2 achieving a power gain of 10 dB, return losses better than 16 dB, noise figure of 3.6-4.9 dB and IIP3 of 0 dBm with 21 mW power consumption. All the implemented circuits and systems in this dissertation are validated, demonstrated and published in several IEEE Journals and Conferences.

Η περιοχή των ραδιοσυχνοτήτων (RF) για σχεδίαση ηλεκτρονικών κυκλωμάτων για τηλεπικοινωνιακά συστήματα αποτελεί ένα χώρο έντονης ερευνητικής δραστηριότητας. Το πρότυπο υπερευρείας ζώνης με την ονομασία Ultra Wideband (UWB), που καταλαμβάνει συχνότητες από 3.1-10.6 GHz, αποτέλεσε αντικείμενο της παρούσης έρευνας με σκοπό την σχεδίαση, κατασκευή και μέτρηση ολοκληρωμένων κυκλωμάτων με έμφαση στα κυκλώματα του μπροστινού τμήματος του UWB δέκτη. Η κατανόηση της λειτουργίας του πομποδέκτη και των παραμέτρων λειτουργίας σε επίπεδο συστήματος αποτέλεσε την αρχική προσέγγιση, με σκοπό τον καθορισμό των προδιαγραφών λειτουργίας των πιο κρίσιμων στοιχείων. Η ανάλυση έλαβε χώρα τόσο σε θεωρητικό επίπεδο όσο και σε επίπεδο εξομοίωσης και τα ηλεκτρονικά στοιχεία των υψηλών συχνοτήτων όπως είναι ο ενισχυτής χαμηλού θορύβου (Low Noise Amplifier - LNA) καθώς και ο μίκτης είναι τα πιο απαιτητικά στη σχεδίαση. Η έρευνα επικεντρώθηκε αρχικά στο κύκλωμα του ενισχυτή χαμηλού θορύβου , το οποίο ευρισκόμενο αμέσως μετά την κεραία λήψης, καλείται να ικανοποιήσει πολλές και αντικρουόμενες μεταξύ τους απαιτήσεις όσον αφορά το εύρος ζώνης, το κέρδος, την κατανάλωση ενέργειας και επιφανείας πυριτίου και το θόρυβο. Στα πλαίσια της μελέτης εξερευνήθηκαν και αξιολογήθηκαν οι υφιστάμενες τοπολογίες που έχουν εμφανιστεί στη βιβλιογραφία και επιλέχθηκαν δύο από αυτές για περεταίρω διερεύνηση. Το πρώτο ολοκληρωμένο που κατασκευάστηκε περιλαμβάνει τρεις ενισχυτές, οι δύο από αυτούς χρησιμοποιούν την τοπολογία κοινής πηγής με φίλτρο εισόδου και πηνίο στην πηγή (inductive source degeneration) και διαφέρουν στον τρόπο μέτρησης, όπου ο ένας ενισχυτής μετράται πάνω στο ολοκληρωμένο (on-wafer probing) και ο έτερος τοποθετείται σε πλακέτα (chip on board). Με τον τρόπο αυτό αποκτάται διαίσθηση όσον αφορά την επίδραση των παρασιτικών που υπεισέρχονται εξαιτίας των διασυνδέσεων των αγωγών (bondwires) μεταξύ ολοκληρωμένου και πλακέτας. Ταυτόχρονα για τον συγκεκριμένο ενισχυτή εφαρμόζεται και στρατηγική προστασίας από ηλεκτροστατικά φορτία (ESD). Ο τρίτος ενισχυτής βασίζεται στην τοπολογία ανάδρασης και αποτέλεσε προϊόν πρωτότυπης έρευνας και χρησιμοποιήθηκαν τεχνικές διεύρυνσης του εύρους ζώνης λειτουργίας με χρήση επαγωγικών στοιχείων. Οι μετρήσεις που επακολούθησαν την κατασκευή αποδείχθηκαν επιτυχείς και κατά κανόνα υπήρξε σύγκλιση με την εξομοίωση. Ο τρίτος ενισχυτής παρουσιάζει την πιο ανταγωνιστική απόδοση και είναι ικανός να λειτουργήσει μέχρι τα 7GHz. Επακόλουθο της κυκλωματικής μελέτης των ενισχυτών χαμηλού θορύβου υπήρξε η εστίαση σε επίπεδο συστήματος για την κατασκευή του συνολικού RF τμήματος του δέκτη σε ολοκληρωμένο και για λειτουργία μέχρι τα 10.6GHz. Το σύστημα περιλαμβάνει τον LNA της τοπολογίας με ανάδραση και στη συνέχεια δύο πανομοιότυπα μονοπάτια αποτελούμενα το καθένα από μίκτη, υψιπερατό φίλτρο και απομονωτή εξόδου στα 50 Ω για τις ανάγκες της μέτρησης. Ως κύριες προκλήσεις ανέκυψαν ο σχεδιασμός του μίκτη και κυρίως της διεπαφής με τον LNA, ο οποίος παρέχει σήμα μονής εξόδου ενώ ο μίκτης λειτουργεί διαφορικά. Στα πλαίσια της διατριβής προτάθηκε μια τεχνική για κύκλωμα μετατροπής μονού σε διαφορικό σήμα (balun), η οποία συνδυαζόμενη με την τοπολογία του μίκτη που επελέγη, ουσιαστικά ενσωματώνεται στο μίκτη και παρέχει διαφορικά σήματα με πολύ καλή ακρίβεια στο πλάτος και τη φάση. Το balun βασίζεται στην τοπολογία του διαφορικού ζεύγους και επεκτείνει πάνω σε αυτήν με χρήση πηνίου που στο κέντρο του παρέχει έναν τρίτο ακροδέκτη διασύνδεσης στην τροφοδοσία. Καταυτόν τον τρόπο λαμβάνει χώρα σύζευξη μεταξύ των φορτίων του balun που εγγυάται την ακρίβεια των μεγεθών που προαναφέρθηκαν. Η τεχνική υποστηρίζεται από ενδελεχή μαθηματική ανάλυση και παρουσιάζονται συγκρίσεις μεταξύ θεωρίας και εξομοίωσης με σύγκλιση μεταξύ των. Ο μίκτης που κατέληξε η έρευνα ανήκει στην κατηγορία της συνδεσμολογίας folded cascode. Δεδομένων επίσης των περιορισμών που υπήρχαν στον εξοπλισμό μέτρησης εφαρμόστηκαν τεχνικές με πιο σημαντική την τροφοδότηση των σημάτων ταλαντωτή τα οποία εσωτερικά του ολοκληρωμένου μετατρέπονται σε διαφορικά και καθοδηγούνται για αποφυγή ασυμμετριών σε ισομήκης μεταλλικές γραμμές μεταφοράς. Σε όλα τα κρίσιμα σημεία έχει προβλεφτεί στρατηγική θωράκισης των υψίσυχνων σημάτων ενώ η τοποθέτηση ενός πολύ μεγάλου αριθμού στοιχείων στο πυρίτιο υπήρξε προϊόν συγκερασμού διαφορετικών απαιτήσεων στη χωροταξία τους με πολυάριθμες τεχνικές και εμπειρικούς κανόνες να έχουν εφαρμοστεί. Η τελική προτεινόμενη αρχιτεκτονική τύπου άμεσης μετατροπής παρόλα τα σχεδιαστικά ρίσκα που είχαν ληφθεί, λειτούργησε επιτυχώς μέχρι και τα 8.5GHz επισφραγίζοντας την συνολική προσπάθεια. / The domain of RF engineering for electronic circuits, targeting the application of telecommunication systems, constitutes a field of intense research activities. The UWB protocol that occupies a frequency spectrum between 3.1 and 10.6 GHz is the subject of the current work which aims to the design, fabrication and measurement of electronic circuits with emphasis put on the receiver’s RF front end. The initial focus of the research work targets the Low Noise Amplifier (LNA) circuit, a demanding and challenging circuit that being at the very front of the receiver’s chain, has to compromise among different and contradictory requirements, namely the extended bandwidth, the gain, the power and chip area consumption and the noise performance. Existing topologies in the literature were explored and classified and two among them were selected for further research. The first fabricated chip includes three LNAs, two of which apply the common source topology with input bandpass filter and inductive source degeneration and their difference lies in the measurement method. One amplifier is measured on wafer while the other is mounted on board. That way, intuition is acquired regarding the effect of the bondwires that act as the interface between the chip and the board. At the same time, ESD protection strategy is applied as the chip is more vulnerable to static currents. The third LNA is based on the feedback topology and constitutes a work of novelty, where bandwidth extension techniques were applied, comprising of inductive elements. The following measurement procedure was successful indicating an upper frequency of operation for the feedback LNA up to 7GHz. The focus of the work after the LNAs was shifted to system level for the implementation of the total RF front end of the receiver up to 10.6GHz. The system comprises an improved version of the feedback LNA followed by two identical paths, each one consisting of a mixer, a high pass filter and an output buffer at 50 Ohm for measurement purpose. The challenges that are mostly highlighted are the mixer design in conjunction with the necessary balun interface from the single ended output of the LNA to the differential mixer. A novel technique is proposed for the balun that builds on the differential pair topology and provides coupling between the load elements that both are implemented with a center tapped inductor. That way the designed balun achieves balanced outputs in terms of amplitude and phase. The technique is supported by mathematical analysis and the comparison between computed and simulated results show convergence. The resulting mixer that includes the balun belongs to the folded cascode differential connection. Moreover, given the limitations of the available measurement equipment, several layout techniques were applied; particularly in the issue of the external LO signal feeding. The two quadrature LO signals are provided in single ended form and traverse the chip by two equal length transmission lines that are separated at the center of the chip and reach the on chip single to differential converters that are placed close to the mixers. In every critical point, care is taken to shield the high frequency signals from interferences. In any case, the placing of a high number of individual elements that have different requirements on the same chip requires for compromises, while layout techniques and rules of thumb have been applied to the maximum extend. The final proposed architecture belongs to the direct conversion category and worked successfully up to the frequency of 8.5GHz. It achieves gain of 25dB, double sideband noise figure of 7dB and power consumption of 62.7 mW.