Com o crescente aumento das funcionalidades dos circuitos integrados, existe um aumento consequente da complexidade do projeto dos mesmos. O fluxo de projeto de circuitos integrados inclui em um de seus passos o roteamento, que consiste em criar fios que interconectam as células do circuito. Devido à complexidade, o roteamento é dividido em global e detalhado. O roteamento global de circuitos VLSI é uma das tarefas mais complexas do fluxo de síntese física, sendo classificado como um problema NP-completo. Neste trabalho, além de realizar um levantamento de trabalhos que utilizam as principais técnicas de paralelismo com o objetivo de acelerar o processamento do roteamento global, foram realizadas análises nos arquivos de benchmark do ISPD 2007/08. Com base nestas análises foi proposto um método que agrupa as redes para então verificar a existência de dependência de dados em cada grupo. Esta verificação de dependência de dados, que chamamos neste trabalho de colisor, tem por objetivo, criar fluxos de redes independentes umas das outras para o processamento em paralelo, ou seja, ajudar a implementação do roteamento independente de redes. Os resultados demonstram que esta separação em grupos, aliada com a comparação concorrente dos grupos, podem reduzir em 67x o tempo de execução do colisor de redes se comparada com a versão sequencial e sem a utilização de grupos. Também foi obtido um ganho de 10x ao comparar a versão com agrupamentos sequencial com a versão paralela. / With the increasing of the functionality of integrated circuits, there is a consequent increase in the complexity of the design. The IC design flow includes the routing in one of its steps, which is to create wires that interconnect the circuit cells. Because of the complexity, routing is divided into global and detailed. The global routing of VLSI circuits is one of the most complex tasks in the flow of physical synthesis and it's classified as an NP-complete problem. In this work, a parallel computing techniques survey was applied to the VLSI global routing in order to accelerate the global routing processing analyzes. This analyzes was performed on the ISPD 2007/08 benchmark files. We proposed a method that groups the networks and then check for data dependence in each group based on these analyzes. This data dependency checking, we call this checking of collider, aims to create flow nets independent of each other for processing in parallel, or help implement the independent routing networks. The results demonstrate that this separation into groups, together with the competitor comparison of groups, can reduce 67x in the collider networks runtime compared with the sequential release and without the use of groups. It was also obtained a gain of 10x when comparing the version with sequential clusters with the parallel version.

Os avanços na microeletrônica contribuíram para a redução de tamanho do nó tecnológico, diminuindo a tensão de limiar e aumentando a freqüência de operação dos sistemas. Embora tenha resultado em ganhos positivos relacionados ao desempenho e ao consumo de energia dos circuitos VLSI, a miniaturização também tem um impacto negativo em termos de confiabilidade dos projetos. À medida que a tecnologia diminui, os circuitos estão se tornando mais suscetíveis a inúmeros efeitos devido à redução da robustez ao ruído externo, bem como ao aumento do grau de incerteza relacionado às muitas fontes de variabilidade. As técnicas de tolerancia a falhas geralmente são usadas para melhorar a robustez das aplicações de segurança crítica. No entanto, as implicações da redução da tecnologia interferem na eficácia de tais abordagem em fornecer a cobertura de falhas desejada. Por esse motivo, este trabalho avaliou a robustez aos efeitos de radiação de diferentes circuitos projetados na tecnologia FinFET sob efeitos de variabilidade. Para determinar as melhores opções de projeto para implementar técnicas de tolerancia a falhas, como os esquemas de Redundância de módulo triplo (TMR) e/ou duplicação com comparação (DWC), o conjunto de circuitos analisados é composto por dez diferentes topologias de porta lógica OR-exclusivo (XOR) e dois circuitos votadores maioritários (MJV). Para investigar o efeito da configuração do gate dos dispositivos FinFET, os circuitos XOR são analisados usando a configuração de double-gate (DG FinFET) e tri-gate (TG FinFET). A variabilidade ambiental, como variabilidade de temperatura e tensão, são avaliadas no conjunto de circuitos analisados. Além disso, o efeito da variabilidade de processo Work-Function Fluctuation (WFF) também é avaliado. A fim de fornecer um estudo mais preciso, o projeto do leiaute dos circuitos MJV usando 7nm FinFET PDK é avaliado pela ferramenta preditiva MUSCA SEP3 para estimar o Soft-Error Rate (SER) dos circuitos considerando as características do leiaute e as camadas de Back-End-Of-Line (BEOL) e Front-End-Of-Line (FEOL) de um nó tecnológico avançado. / Advances in microelectronics have contributed to the size reduction of the technological node, lowering the threshold voltage and increasing the operating frequency of the systems. Although it has positive outcomes related to the performance and power consumption of VLSI circuits, it does also have a strong negative impact in terms of the reliability of designs. As technology scales down, the circuits are becoming more susceptible to numerous effects due to the reduction of robustness to external noise as well as the increase of uncertainty degree related to the many sources of variability. Faulttolerant techniques are usually used to improve the robustness of safety critical applications. However, the implications of the scaling of technology have interfered against the effectiveness of fault-tolerant approaches to provide the fault coverage. For this reason, this work has evaluated the radiation robustness of different circuits designed in FinFET technology under variability effects. In order to determine the best design options to implement fault-tolerant techniques such as the Triple-Module Redundancy (TMR) and/or Duplication with Comparison (DWC) schemes, the set of analyzed circuits is composed of ten different exclusive-OR (XOR) logic gate topologies and two majority voter (MJV) circuits. To investigate the effect of gate configuration of FinFET devices, the XOR circuits is analyzed using double-gate configuration (DG FinFET) and tri-gate configuration (TG FinFET). Environmental Variability such as Temperature and Voltage Variability are evaluated in the set of analyzed circuits. Additionally, the process-related variability effect Work-Function Fluctuation (WFF) is also evaluated. In order to provide a more precise study, the layout design of the MJV circuits using a 7nm FinFET PDK is evaluated by the predictive MUSCA SEP3 tool to estimate the Soft-Error Rate (SER) of the circuits considering the layout contrainsts and Back-End-Of-Line (BEOL) and Front-End-Of-Line (FEOL) layers of an advanced technology node.

La bioélectronique utilise des signaux électriques pour interagir avec des systèmes biologiques. Les capteurs qui permettent la lecture électrique de marqueurs de maladies importantes et les implants/stimulateurs utilisés pour la détection et le traitement d'activité cellulaire pathologique ne sont que quelques exemples de ce que cette technologie peut offrir. Du fait de leurs propriétés électro-actives et mécaniques fascinantes, l'électronique organique ou les matériaux conjugués π ont été largement exploités dans le domaine de la bioélectronique. Le mélange intéressant entre conductivité électronique et ionique de ces polymères conducteurs permet le couplage entre les charges électroniques présentent dans le volume des films organiques avec les flux ioniques du milieu biologique. Le matériau prototypique de la bioélectronique organique est le polymère conducteur poly(3,4-éthylènedioxythiophène) (PEDOT) dopé avec du polystyrène sulfonate (PSS). Dans ce rapport, nous étudierons une approche pour moduler les propriétés mécaniques, électriques et électrochimiques du PEDOT: PSS et étudier leur impact sur la performance des transistors électrochimiques organiques. Par ailleurs, nous évaluerons l'effet de la micro-structuration et du nano-patterning sur l'impédance électrochimique des électrodes en or recouvertes de PEDOT: PSS utiles pour de futurs enregistrements et stimulations neurales. Enfin, nous démontrerons l'utilisation du PEDOT:PSS à micro-motifs pour l'adhésion et la migration de cellules. / Bioelectronics uses electrical signals to interact with biological systems. Sensors that allow for electrical read-out of important disease markers, and implants/stimulators used for the detection and treatment of pathological cellular activity are only a few examples of what this technology can offer. Due to their intriguing electroactive and mechanical properties, organic electronics or π-conjugated materials have been extensively explored regarding their use in bioelectronics applications. The attractive mixed electronic/ionic conductivity feature of conducting polymers enables coupling between the electronic charges in the bulk of the organic films with ion fluxes in biological medium. The prototypical material of organic bioelectronics is the conducting polymer poly(3,4-ethylenedioxythiophene) (PEDOT) doped with polystyrene sulfonate (PSS). PEDOT:PSS is commercially available, water-dispersible conjugated polymer complex that can be cast into films of high hole and cation conductivity, good charge storage capacity, biocompatibility, and chemical stability. In the present work we investigate an approach to tailor the mechanical, electrical, and electrochemical properties of PEDOT:PSS and study their impact on the performance of organic electrochemical transistors. In addition, we study the effect of micro-structuring and nano-patterning on the electrochemical impedance of PEDOT:PSS- coated gold electrodes for future neural recordings and stimulation. Moreover we demonstrate the use of micro-patterned PEDOT:PSS in cell adhesion and migration.

Les Dispositifs Médicaux d’Injection (DMI) se développent de plus en plus. De nouveaux dispositifs apportent des innovations en terme de performances et d’utilisation par rapport aux seringues classiques. Le DMI développé par Eveon est un dispositif bio-inspiré possédant des capteurs, une micropompe, un flacon et une aiguille. Il permet une injection automatique, précise au microlitre garantissant une faible perte de liquide médicamenteux grâce aux techniques de miniaturisation utilisées dans la fabrication des microsystèmes. En effet, une micropompe à membrane en silicium intégrant des capteurs a été réalisée par des procédés issus de la microélectronique. Deux types d’actionneurs ont été couplés à la membrane : un actionneur bimétallique intégré et un actionneur piezoélectrique externe. Dans le cas de l’actionneur bimétallique, des thermo-résistances ont été conçues, fabriquées et caractérisées pour permettre de mesurer le profil thermique de la membrane lors de l’actionnement avec une erreur de 5%. Dans le cas de l’actionneur piezoélectrique externe, des piezorésistances ont été intégrées selon l’axe radial de la membrane afin de contrôler le profil de contraintes dans la membrane, asservir l’actionneur en fonction de la contre-pression et maximiser les caractéristiques de la pompe. Afin d’assurer la délivrance d’une dose précise de médicament, un capteur de débit est intégré dans les canaux microfluidiques de la micropompe. Ce capteur innovant permet de détecter des débits de liquide dans la gamme spécifiée par les dispositifs médicaux d’injection, à savoir une plage de débit allant de 0.5mL/min à 4mL/min. / Injection Medical Devices are more and more developed. New devices bring innovations in terms of performances and use for classical syringes. Eveon develops a bio-inspired device including some sensors, a micropump, a reservoir and a needle. This automatic injection can be microliter precise with a small loss of medical liquid thanks to microfabrication techniques used for microsystems. Indeed, a silicon membrane micropump integrating sensors was fabricated using processes from microelectronic fabrication. Two actuation types were coupled to the membrane: an integrated bimetallic actuator and an external piezoelectric actuator. In the case of the bimetallic actuator, thermo-resistances were designed, fabricated and characterized to measure the thermal profile of the membrane during the actuation with a 5% error. In the case of piezoelectric actuation, piezoresistances were integrated within the membrane profile along the radial axis to control its stress, feedback the actuation as a function of the pressure and maximize the pump characteristics. To ensure that the dose of medicine was delivered, a flow rate sensor was integrated in the microfluidic channels of the micropump. This innovative sensor can detect liquid flow rate in a range specified for injection medical devices, namely flow rates from 0.5mL/min to 4mL/min.

L'éco-conception est un processus permettant aux entreprises industrielles d'assumer leur responsabilité relative aux impacts générés par leurs produits. Les contraintes liées aux impacts environnementaux sont intégrées dans les stades avancés de la conception. Du fait de ses spécificités, tant au niveau de la structure du produit que de la complexité des processus de conception, l'industrie microélectronique s'est trouvée jusqu'alors en marge de considérations avancées sur l'impact de ses produits. L'objectif du travail de recherche est de définir une méthodologie d'éco-conception dédiée à la microélectronique permettant d'identifier les méthodes, outils et indicateurs susceptibles d'être déployés dans les départements de R&D. La stratégie associée vise à accroître la sensibilité environnementale des concepteurs et à les conduire à trouver des alternatives influant positivement sur l'environnement. Notre méthodologie repose sur une plateforme méthodologique intégrant plusieurs outils, chacun dédié à une activité indépendante de la conception de produits microélectroniques. L'évaluation environnementale est basée sur l'analyse de cycle de vie (ACV). Dans les phases préliminaires de conception, la connaissance du produit (structure, propriétés et performances) est limitée, alors la modélisation de son cycle de vie est réalisée à l'aide « d'ACV-simplifiée » : cela consiste à prédire l'impact d'un produit en développement grâce à des mécanismes d'adaptation par analogie basés sur l'étude des générations précédentes. En plus de solutions techniques appropriées, l'intégration de l'éco-conception dans une entreprise nécessite certains changements organisationnels : une modification du processus de conception a été proposée ainsi que des recommandations pour l'intégration d'un système de gestion de l'environnement orienté sur les produits. / Eco-design represents a natural process for industries wishing to fulfil their role in safeguarding environment and resources. The constraint linked to impacts becomes a decisive factor which can be systematically integrated in the early stages of products development. Because of chips specificities, both in structure and complexity of design process, microelectronic industry has been up to now out of advanced considerations related to chips environnemental performances. Our target was to define an eco-design methodology dedicated to microelectronic sector including the identification of methods, tools and indicators which have the highest chance to be deployed in R&D departments. The strategy aims to increase designers' environmental consciousness and drive them to explore innovative opportunities that can positively impact the environment during design phase. Our methodology relies on a platform integrating three tools, each one of them dedicated to a part of chip design. Environmental analysis is based on Life Cycle Assessment (LCA). In the preliminary stages of design, knowledge on product (structure, properties and performances) is limited so the evaluation is assessed using “Quick LCA”: it consists in predicting the environmental footprint of an under-development product thanks to adaptive mechanism based on the evaluation of previous generations. In addition to technical solutions, an optimized integration of an innovative process such as eco-design requires organizational changes into the company: a proposal for internal design process modification was done including recommendations for integration of a product-oriented management system.

D’une part, les fluctuations et le bruit basse fréquence (BF) dans les dispositifs MOS ont été le sujet de recherche intensive durant ces dernières années. Le bruit BF devient une inquiétude majeure pour la réduction continuelle de la dimension des transistors car le bruit 1/f augmente comme l’inverse de la surface des transistors. Le bruit BF et les fluctuations en excès pourraient constituer une limitation sérieuse du fonctionnement des circuits analogiques et numériques. Le bruit 1/f est également d'importance primordiale pour les applications de circuit RF où il provoque le bruit de phase dans les oscillateurs ou les multiplexeurs. Le développement des technologies submicroniques CMOS a conduit à l’observation d’un nouveau type de bruits, i.e. signaux télégraphiques aléatoires (RTS), entrainant de grandes amplitudes de fluctuations à l’heure actuelle, qui peuvent compromettre la fonctionnalité des circuits. D'autre part, la variabilité statistique dans les caractéristiques de transistor est l'un des défis principaux pour les prochaines générations technologiques. La connaissance détaillée des sources de variabilité est extrêmement importante pour la conception et la fabrication des dispositifs résistants à la variabilité. On constate que la dispersion des valeurs de courant de drain des dispositifs n-MOS plutôt petits de la technologie 28 nm est presque deux décades. Cela résulte de l'impact des dopants aléatoires, de la rugosité de bord des lignes et les variations d'épaisseur d'oxyde, qui est plutôt bien compris, ainsi que du rôle du matériau de grille, en poly silicium ou en métal seulement, qui n’a été que récemment étudié dans les simulations. La confirmation et la quantification expérimentales de la contribution du bruit et des fluctuations BF manquent toujours. En outre, l'étude de la variabilité du bruit BF et de sa relation avec les autres facteurs des variations des dispositifs n'a été jamais effectuée. Par conséquent, les défis de recherches et les objectifs de cette thèse sont centrés vers les études des fluctuations basses fréquences et du bruit dans les technologies CMOS 32nm et au-delà. Plus spécifiquement, le bruit BF sera étudié avec trois objectifs : i) la caractérisation détaillée du bruit BF des nouvelles technologies CMOS comportant des grilles avec high-k/métal, des poches de canal etc., ii) le changement des paramètres de bruit BF des différentes technologies et iii) l'impact du bruit BF et des fluctuations RTS en tant que sources de variabilité pour des applications de circuit analogique et numérique. Le premier objectif adressera l'origine des fluctuations de BF dans des dispositifs CMOS en termes de densité de piège et de localisation des défauts dans le diélectrique de grille et avec la longueur du canal pour différentes architectures (poche, canal de germanium, FD-SOI etc.). La deuxième partie considérera la variabilité du bruit BF résultant de la dispersion énorme des sources de bruit de dispositif à dispositif ; ceci sera conduit grâce à des mesures statistiques des caractéristiques de bruit de BF en fonction de la surface des dispositifs et des générations technologiques. Le troisième objective se concentrera sur l'impact du bruit de BF ou des fluctuations RTS sur le fonctionnement des circuits élémentaires (inverseur, cellule SRAM) et considérés en tant que source temporelle de variabilité. Nous allons aborder ces trois questions une après l’autre dans les paragraphes suivants. / Low frequency (LF) noise and fluctuations in MOS devices has been the subject of intensive research during the past years. The LF noise is becoming a major concern for continuously scaled down devices, since the 1/f noise increases as the reciprocal of the device area. Excessive low frequency noise and fluctuations could lead to serious limitation of the functionality of the analog and digital circuits. The 1/f noise is also of paramount importance in RF circuit applications where it gives rise to phase noise in oscillators or multiplexors. The development of submicronic CMOS technologies has led to the onset of new type of noises, i.e. random telegraph signals (RTS), yielding large current fluctuations, which can jeopardize the circuit functionality. However, the statistical variability in the transistor characteristics is one of the major challenges for upcoming technological nodes. The detailed knowledge of variability sources is extremely important for the design and manufacturing of variability resistant devices. Whereas the impact of random dopants, line edge roughness and oxide thickness variations is relatively well understood, the role of the polysilicon or metal gate material has only lately been investigated in simulations and experimental confirmation and quantification of its contribution is still lacking. In addition, the study of LFN variability behavior and maybe its relation with the other factors of device variations has never been done. Therefore, the research challenges and objectives of this thesis are centered towards the studies of low frequency fluctuations and noise in 32 nm CMOS technologies and beyond. More specifically, the objectives of the LF noise investigation is summarized in the following points: i) Detailed LF noise characterization of new CMOS technologies featuring high-κ metal gate stacks, channel pockets etc, ii) change of LF noise parameters from different technologies and iii) impact of LF noise and RTS fluctuations as a variability sources for analog and digital circuits. The first objective addresses the origin of the LF fluctuations in CMOS devices in terms of trap density and defect localization in the gate dielectric and along the channel for various architectures (pocket, Ge channel, FD-SOI etc). The second objective considers the LF noise variability resulting from huge dispersion of noise sources from device to device; this is conducted owing to statistical measurements of LF noise characteristics as a function of device area and technological splits. The third issue is focused on the impact of LF noise or RTS fluctuations on the operation of elementary circuits (inverter, SRAM cell) regarded as temporal variability source.

Este trabalho será focado no problema de posicionamento de células lógicas em circuitos integrados. Neste problema necessitamos organizar as portas lógicas reduzindo o comprimento dos fios que as conectam da melhor forma possível. Para entender o problema e as soluções existentes é descrita uma explanação sobre técnicas e algoritmos que são utilizados atualmente ou que são historicamente importantes, de forma a conduzir o texto para as técnicas apresentadas neste trabalho. As técnicas que serão apresentadas neste trabalho têm objetivos individualmente diferentes, porém conduzem a novos resultados e perspectivas em posicionamento. Todas as técnicas são baseadas na modificação e análise do grafo do posicionamento. Neste trabalho serão apresentadas quatro técnicas para melhorar a solução do problema de posicionamento. O primeiro trabalho a ser apresentado será a Critical Star que aplicado alguns nodos e arestas extras no grafo original para reduzir os caminhos críticos. A segunda técnica é a Logical Core I, ela traz um novo método de análise da dificuldade de posicionar um circuito VLSI. A terceira técnica, que tem forte conexão com a segunda, é a Logical Core II, mais focada em tempo de execução da técnica, ela gera um vetor com todas as dificuldades de posicionar cada célula no circuito. As duas técnicas aumentam o conhecimento do posicionador a respeito do problema e com isso vão de encontro a um ponto muito importante e ainda pouco abordado, a evolução da controlabilidade no posicionamento. A quarta técnica que será apresentada é a Logical Cluster. É uma técnica baseada na Logical Core II, e foi desenvolvida para otimizar os posicionadores já existentes no estado da arte. A técnica é muito eficiente e reduz o tempo de execução do posicionamento e muitas vezes reduz o comprimento de fio. / This work is focused on placement problem of VLSI circuits. The goal is organize the logic gates reducing the total wirelength that connect them. A non-effective placement assignment will not only affect the circuit performance but might also make it non-manufacturable by producing excessive wirelength. Then the next step in the assembly line, the routing problem could be insolvable. In this work will be presents four differents techniques. The techniques are based on changing the graph to improve the placement results. The first one is the Critical Star that applies some extra nodes and edges to reduce the critical paths. The second algorithm is the Logical Core I which brings a new method to analyze the circuit hardness to place a circuit. The third algorithm is called Logical Core II and the focus is generate a vector with hardness to place each cell in the circuit, and increasing the placer information about the problem. The Logical Core I and II, both improving the possibility to compare the hardnesses, in different abstraction levels, and improve the placement controllability. The fourth algorithm is a fast algorithm, based on use the Logical Core II, it creates an effective clustering technique to improve the state-of-art placers results. Reducing the runtime and sometimes improving the wirelength results.

Os avanços na microeletrônica contribuíram para a redução de tamanho do nó tecnológico, diminuindo a tensão de limiar e aumentando a freqüência de operação dos sistemas. Embora tenha resultado em ganhos positivos relacionados ao desempenho e ao consumo de energia dos circuitos VLSI, a miniaturização também tem um impacto negativo em termos de confiabilidade dos projetos. À medida que a tecnologia diminui, os circuitos estão se tornando mais suscetíveis a inúmeros efeitos devido à redução da robustez ao ruído externo, bem como ao aumento do grau de incerteza relacionado às muitas fontes de variabilidade. As técnicas de tolerancia a falhas geralmente são usadas para melhorar a robustez das aplicações de segurança crítica. No entanto, as implicações da redução da tecnologia interferem na eficácia de tais abordagem em fornecer a cobertura de falhas desejada. Por esse motivo, este trabalho avaliou a robustez aos efeitos de radiação de diferentes circuitos projetados na tecnologia FinFET sob efeitos de variabilidade. Para determinar as melhores opções de projeto para implementar técnicas de tolerancia a falhas, como os esquemas de Redundância de módulo triplo (TMR) e/ou duplicação com comparação (DWC), o conjunto de circuitos analisados é composto por dez diferentes topologias de porta lógica OR-exclusivo (XOR) e dois circuitos votadores maioritários (MJV). Para investigar o efeito da configuração do gate dos dispositivos FinFET, os circuitos XOR são analisados usando a configuração de double-gate (DG FinFET) e tri-gate (TG FinFET). A variabilidade ambiental, como variabilidade de temperatura e tensão, são avaliadas no conjunto de circuitos analisados. Além disso, o efeito da variabilidade de processo Work-Function Fluctuation (WFF) também é avaliado. A fim de fornecer um estudo mais preciso, o projeto do leiaute dos circuitos MJV usando 7nm FinFET PDK é avaliado pela ferramenta preditiva MUSCA SEP3 para estimar o Soft-Error Rate (SER) dos circuitos considerando as características do leiaute e as camadas de Back-End-Of-Line (BEOL) e Front-End-Of-Line (FEOL) de um nó tecnológico avançado. / Advances in microelectronics have contributed to the size reduction of the technological node, lowering the threshold voltage and increasing the operating frequency of the systems. Although it has positive outcomes related to the performance and power consumption of VLSI circuits, it does also have a strong negative impact in terms of the reliability of designs. As technology scales down, the circuits are becoming more susceptible to numerous effects due to the reduction of robustness to external noise as well as the increase of uncertainty degree related to the many sources of variability. Faulttolerant techniques are usually used to improve the robustness of safety critical applications. However, the implications of the scaling of technology have interfered against the effectiveness of fault-tolerant approaches to provide the fault coverage. For this reason, this work has evaluated the radiation robustness of different circuits designed in FinFET technology under variability effects. In order to determine the best design options to implement fault-tolerant techniques such as the Triple-Module Redundancy (TMR) and/or Duplication with Comparison (DWC) schemes, the set of analyzed circuits is composed of ten different exclusive-OR (XOR) logic gate topologies and two majority voter (MJV) circuits. To investigate the effect of gate configuration of FinFET devices, the XOR circuits is analyzed using double-gate configuration (DG FinFET) and tri-gate configuration (TG FinFET). Environmental Variability such as Temperature and Voltage Variability are evaluated in the set of analyzed circuits. Additionally, the process-related variability effect Work-Function Fluctuation (WFF) is also evaluated. In order to provide a more precise study, the layout design of the MJV circuits using a 7nm FinFET PDK is evaluated by the predictive MUSCA SEP3 tool to estimate the Soft-Error Rate (SER) of the circuits considering the layout contrainsts and Back-End-Of-Line (BEOL) and Front-End-Of-Line (FEOL) layers of an advanced technology node.

Com o crescente aumento das funcionalidades dos circuitos integrados, existe um aumento consequente da complexidade do projeto dos mesmos. O fluxo de projeto de circuitos integrados inclui em um de seus passos o roteamento, que consiste em criar fios que interconectam as células do circuito. Devido à complexidade, o roteamento é dividido em global e detalhado. O roteamento global de circuitos VLSI é uma das tarefas mais complexas do fluxo de síntese física, sendo classificado como um problema NP-completo. Neste trabalho, além de realizar um levantamento de trabalhos que utilizam as principais técnicas de paralelismo com o objetivo de acelerar o processamento do roteamento global, foram realizadas análises nos arquivos de benchmark do ISPD 2007/08. Com base nestas análises foi proposto um método que agrupa as redes para então verificar a existência de dependência de dados em cada grupo. Esta verificação de dependência de dados, que chamamos neste trabalho de colisor, tem por objetivo, criar fluxos de redes independentes umas das outras para o processamento em paralelo, ou seja, ajudar a implementação do roteamento independente de redes. Os resultados demonstram que esta separação em grupos, aliada com a comparação concorrente dos grupos, podem reduzir em 67x o tempo de execução do colisor de redes se comparada com a versão sequencial e sem a utilização de grupos. Também foi obtido um ganho de 10x ao comparar a versão com agrupamentos sequencial com a versão paralela. / With the increasing of the functionality of integrated circuits, there is a consequent increase in the complexity of the design. The IC design flow includes the routing in one of its steps, which is to create wires that interconnect the circuit cells. Because of the complexity, routing is divided into global and detailed. The global routing of VLSI circuits is one of the most complex tasks in the flow of physical synthesis and it's classified as an NP-complete problem. In this work, a parallel computing techniques survey was applied to the VLSI global routing in order to accelerate the global routing processing analyzes. This analyzes was performed on the ISPD 2007/08 benchmark files. We proposed a method that groups the networks and then check for data dependence in each group based on these analyzes. This data dependency checking, we call this checking of collider, aims to create flow nets independent of each other for processing in parallel, or help implement the independent routing networks. The results demonstrate that this separation into groups, together with the competitor comparison of groups, can reduce 67x in the collider networks runtime compared with the sequential release and without the use of groups. It was also obtained a gain of 10x when comparing the version with sequential clusters with the parallel version.

Com o crescente aumento das funcionalidades dos circuitos integrados, existe um aumento consequente da complexidade do projeto dos mesmos. O fluxo de projeto de circuitos integrados inclui em um de seus passos o roteamento, que consiste em criar fios que interconectam as células do circuito. Devido à complexidade, o roteamento é dividido em global e detalhado. O roteamento global de circuitos VLSI é uma das tarefas mais complexas do fluxo de síntese física, sendo classificado como um problema NP-completo. Neste trabalho, além de realizar um levantamento de trabalhos que utilizam as principais técnicas de paralelismo com o objetivo de acelerar o processamento do roteamento global, foram realizadas análises nos arquivos de benchmark do ISPD 2007/08. Com base nestas análises foi proposto um método que agrupa as redes para então verificar a existência de dependência de dados em cada grupo. Esta verificação de dependência de dados, que chamamos neste trabalho de colisor, tem por objetivo, criar fluxos de redes independentes umas das outras para o processamento em paralelo, ou seja, ajudar a implementação do roteamento independente de redes. Os resultados demonstram que esta separação em grupos, aliada com a comparação concorrente dos grupos, podem reduzir em 67x o tempo de execução do colisor de redes se comparada com a versão sequencial e sem a utilização de grupos. Também foi obtido um ganho de 10x ao comparar a versão com agrupamentos sequencial com a versão paralela. / With the increasing of the functionality of integrated circuits, there is a consequent increase in the complexity of the design. The IC design flow includes the routing in one of its steps, which is to create wires that interconnect the circuit cells. Because of the complexity, routing is divided into global and detailed. The global routing of VLSI circuits is one of the most complex tasks in the flow of physical synthesis and it's classified as an NP-complete problem. In this work, a parallel computing techniques survey was applied to the VLSI global routing in order to accelerate the global routing processing analyzes. This analyzes was performed on the ISPD 2007/08 benchmark files. We proposed a method that groups the networks and then check for data dependence in each group based on these analyzes. This data dependency checking, we call this checking of collider, aims to create flow nets independent of each other for processing in parallel, or help implement the independent routing networks. The results demonstrate that this separation into groups, together with the competitor comparison of groups, can reduce 67x in the collider networks runtime compared with the sequential release and without the use of groups. It was also obtained a gain of 10x when comparing the version with sequential clusters with the parallel version.