Global ETD Search

21	Low-power high-resolution image detection Merchant, Caleb 09 August 2019 (has links) Many image processing algorithms exist that can accurately detect humans and other objects such as vehicles and animals. Many of these algorithms require large amounts of processing often requiring hardware acceleration with powerful central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), etc. Implementing an algorithm that can detect objects such as humans at longer ranges makes these hardware requirements even more strenuous as the numbers of pixels necessary to detect objects at both close ranges and long ranges is greatly increased. Comparing the performance of different low-power implementations can be used to determine a trade-off between performance and power. An image differencing algorithm is proposed along with selected low-power hardware that is capable of detected humans at ranges of 500 m. Multiple versions of the detection algorithm are implemented on the selected hardware and compared for run-time performance on a low-power system. object detection image detection low-power long-range high-resolution image differencing frame differencing morphology multi-threading hardware acceleration ARM Vivante NXP GPU CPU
22	Exploring feasibility of reinforcement learning flight route planning / Undersökning av använding av förstärkningsinlärning för flyruttsplannering Wickman, Axel January 2021 (has links) This thesis explores and compares traditional and reinforcement learning (RL) methods of performing 2D flight path planning in 3D space. A wide overview of natural, classic, and learning approaches to planning s done in conjunction with a review of some general recurring problems and tradeoffs that appear within planning. This general background then serves as a basis for motivating different possible solutions for this specific problem. These solutions are implemented, together with a testbed inform of a parallelizable simulation environment. This environment makes use of random world generation and physics combined with an aerodynamical model. An A* planner, a local RL planner, and a global RL planner are developed and compared against each other in terms of performance, speed, and general behavior. An autopilot model is also trained and used both to measure flight feasibility and to constrain the planners to followable paths. All planners were partially successful, with the global planner exhibiting the highest overall performance. The RL planners were also found to be more reliable in terms of both speed and followability because of their ability to leave difficult decisions to the autopilot. From this it is concluded that machine learning in general, and reinforcement learning in particular, is a promising future avenue for solving the problem of flight route planning in dangerous environments. SAAB flight route planning autorouting auto-routing auto routing AI machine learning fighter jet convolution PPO DQN Astar A* C++ Python LibTorch PyTorch multi threading multi-threading simulation aerodynamics world generation Perlin noise investigation reward Flygplanering flygruttsplannering maskininlärning AI SAAB faltning faltningslager belöning
23	Towards Low-Complexity Scalable Shared-Memory Architectures Zeffer, Håkan January 2006 (has links) <p>Plentiful research has addressed low-complexity software-based shared-memory systems since the idea was first introduced more than two decades ago. However, software-coherent systems have not been very successful in the commercial marketplace. We believe there are two main reasons for this: lack of performance and/or lack of binary compatibility.</p><p>This thesis studies multiple aspects of how to design future binary-compatible high-performance scalable shared-memory servers while keeping the hardware complexity at a minimum. It starts with a software-based distributed shared-memory system relying on no specific hardware support and gradually moves towards architectures with simple hardware support.</p><p>The evaluation is made in a modern chip-multiprocessor environment with both high-performance compute workloads and commercial applications. It shows that implementing the coherence-violation detection in hardware while solving the interchip coherence in software allows for high-performing binary-compatible systems with very low hardware complexity. Our second-generation hardware-software hybrid performs on par with, and often better than, traditional hardware-only designs.</p><p>Based on our results, we conclude that it is not only possible to design simple systems while maintaining performance and the binary-compatibility envelope, it is often possible to get better performance than in traditional and more complex designs.</p><p>We also explore two new techniques for evaluating a new shared-memory design throughout this work: adjustable simulation fidelity and statistical multiprocessor cache modeling.</p> shared memory distributed shared memory hardware-software trade-off software coherence coherence profiling remote access cache chip multiprocessor simultaneous multi threading simulation workload characterization statistical cache model Computer engineering Datorteknik
24	Towards Low-Complexity Scalable Shared-Memory Architectures Zeffer, Håkan January 2006 (has links) Plentiful research has addressed low-complexity software-based shared-memory systems since the idea was first introduced more than two decades ago. However, software-coherent systems have not been very successful in the commercial marketplace. We believe there are two main reasons for this: lack of performance and/or lack of binary compatibility. This thesis studies multiple aspects of how to design future binary-compatible high-performance scalable shared-memory servers while keeping the hardware complexity at a minimum. It starts with a software-based distributed shared-memory system relying on no specific hardware support and gradually moves towards architectures with simple hardware support. The evaluation is made in a modern chip-multiprocessor environment with both high-performance compute workloads and commercial applications. It shows that implementing the coherence-violation detection in hardware while solving the interchip coherence in software allows for high-performing binary-compatible systems with very low hardware complexity. Our second-generation hardware-software hybrid performs on par with, and often better than, traditional hardware-only designs. Based on our results, we conclude that it is not only possible to design simple systems while maintaining performance and the binary-compatibility envelope, it is often possible to get better performance than in traditional and more complex designs. We also explore two new techniques for evaluating a new shared-memory design throughout this work: adjustable simulation fidelity and statistical multiprocessor cache modeling. shared memory distributed shared memory hardware-software trade-off software coherence coherence profiling remote access cache chip multiprocessor simultaneous multi threading simulation workload characterization statistical cache model Computer engineering Datorteknik
25	The modernization of a DOS-basedtime critical solar cell LBICmeasurement system. Hjern, Gunnar January 2019 (has links) LBIC is a technique for scanning the local quantum efficiency of solar cells. This kind of measurements needs a highly specialized, and time critical controlling software. In 1996 the client, professor Markus Rinio, constructed an LBIC system, and wrote the controlling software as a Turbo-Pascal 7.0 application, running under the MS-DOS 6.22 operating system. By now (2018) both the software and several hardware components are in dire need to be modernized. This thesis thoroughly describes several important aspects of this work, and the considerations needed for a successful result. This includes both very foundational choices about the software architecture, the choice of suitable operating system, the threading model, and the adaptation to new hardware with vastly different behavior. The project also included a new hardware module for position reports and instrument triggering, as well as several adaptations to transform the DOS-based LBIC software into a pleasant modern GUI application. Pascal programming language Linux operating system real-time PREEMPT_RT patch Free Pascal compiler Lazarus multi-threading computer controlled measurements false color map refactoring software modernization adaptation layer MS-DOS GPIB IEEE-488 silicon solar cell quantum efficiency LBIC electron recombination serial communication micro-controller ISR incremental encoder lock-in amplifier trans-impedance amplifier triggered measurement Computer and Information Sciences Data- och informationsvetenskap

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