Esse trabalho teve como objetivo a produção e a caracterização elétrica de filmes finos de telureto com nanopartículas de ouro, depositados pela técnica sputtering, para aplicação em dispositivos de memória. Os filmes finos foram produzidos a partir de alvos cerâmicos de telureto (TeO2-ZnO) e foram nucleadas nanopartículas de ouro para observar sua influência no comportamento de memória. Foi desenvolvida metodologia adequada para a nucleação das nanopartículas por meio de tratamento térmico. Foram produzidos filmes com diferentes concentrações e tamanhos de nanopartículas e diferentes fluxos de oxigênio durante a deposição. Os filmes foram caracterizados por técnicas como Microscopia Eletrônica de Transmissão (TEM), Perfilometria, Espectrometria por Retroespalhamento de Rutherford (RBS) e extração de curvas de Corrente x Tensão (I-V). Por meio das medidas I-V foi possível identificar as melhores condições para aplicações em memória e correlacioná-las com as variáveis de processo estudadas. Resultados obtidos mostraram que a melhor condição para aplicações em memória não volátil foi encontrada em filmes com 100 nm de espessura e depositados com fluxo de oxigênio de 1 sccm, abertura do shutter em 50 e tratados termicamente por 10 ou 20 horas à 325 ºC. Nesses casos, foi observado um abrupto aumento na corrente (4 ordens de grandeza) em aproximadamente 6,5 V para 10 horas de tratamento térmico e 3,5 V para 20 horas de tratamento térmico, indicando a transição do estado inicial de baixa condutividade para outro de alta condutividade. As nanopartículas de ouro proporcionam maior capacidade de armazenamento de elétrons e não favorecem o transporte de corrente através do isolante; elas atuam como armadilhas para as cargas elétricas, o que reduz a corrente de fuga para níveis mais baixos. Foi estudada a influência do diâmetro e da concentração volumétrica das nanopartículas de ouro no valor da tensão elétrica associada à transição abrupta da corrente. Este parâmetro desempenha um papel importante no efeito de memória, pois determina a facilidade/dificuldade em se preencher e saturar as armadilhas (nanopartículas de ouro) com elétrons. Os materiais estudados neste trabalho mostraram-se promissores para aplicações em dispositivos de memória não volátil e possuem características semelhantes aos materiais orgânicos usados para o referido fim. / This work has the objective to fabricate and characterize electrically tellurite thin films containing gold nanoparticles, deposited by the sputtering technique, for application in memory devices. Thin films were produced from ceramic tellurite targets and gold nanoparticles were nucleated in order to observe their influence on memory behavior. An appropriate method was developed for the nucleation of the nanoparticles by means of heat treatment. Films with different nanoparticles sizes and concentration and different oxygen fluxes during the deposition, were produced. The films were characterized by techniques such as Transmission Electron Microscopy (TEM), Profilometry, Rutherford Backscatter Spectrometry (RBS) and current x voltage (I-V) curves. Using I-V measurements, it was possible to identify the best conditions for memory applications and correlate them with the process variables studied. The results showed that the best condition for memory applications was found in films with 100 nm thickness and deposited with oxygen flow of 1 sccm, opening shutter in 50 and heat treated for 10 or 20 hours at 325 ºC. In these cases, current abrupt increase (4 orders of magnitude) was observed at about 6.5 V for 10 hours of heat treatment and 3.5 V for 20 hours of heat treatment, indicating the transition from high impedance state to low impedance state. Gold nanoparticles provide a larger electron storage capability, and do not favor the electric transport through the insulator; they act as traps for electrical charges, which reduces the leak current to lower levels. It was studied the influence of the gold nanoparticles diameter and volumetric concentration on the voltage associated to the abrupt current. These parameters played an important role in the memory effect, as they determined the facility/difficulty to fill and saturate the traps (Au nanoparticles) with electrons. The materials studied in the present work, based on TeO2-ZnO thin films with Au nanoparticles, are promising for applications in nonvolatile memory device with similar characteristics to organic materials used for the same purpose.

Thermal constraints and the quantum limit will soon put a boundary on the scale of new micro and nano magnetoelectronic devices. This necessitates a push into the limits of harnessable natural phenomena to facilitate a post-Moore’s era of design. Requirements for thermodynamic stability at room temperature, fast (Ghz) switching, and low energy cost narrow the list of candidates. Molecular electronic frontier orbital structure of some d-block transition metal ions in crystal fields will deform in response to their local energetic environment, giving rise to the eg and t2g suborbitals. More specifically, in an mononuclear Fe(II) complex, the energetic scale between these two orbitals yields an S=0 low spin diamagnetic state and an S=2 high spin paramagnetic state. Spin crossover complex [Fe{H2B (pz) 2 }2 (bipy)] will show locking of its spin state well above the transition temperature, with an accompanied change of conductivity, when placed in a polar environment. Here we show voltage controllable, room temperature, stable locking of the spin state, and the corresponding conductivity change, when molecular thin films of [Fe{H2B (pz) 2 }2 (bipy)] are deposited on a ferroelectric polyvinylidene fluoride hexafluropropylene substrate. This opens the door to the creation of a thermodynamically stable, room temperature, molecular multiferroic gated voltage device.

This diploma thesis presents experimental evidence of a theoretical concept which predicts the self-organization of delta-layers of silicon nanoclusters in the buried oxide of a MOS-like structure. This approach of "bottom-up" structuring might be of eminent importance in view of future semiconductor memory devices. Unconventionally, a 15nm thin SiO2 layer, which is enclosed by a 50nm poly-Si capping layer and the Si substrate, is irradiated with Si+ ions. Ion impact drives the system to a state far from thermodynamic equilibrium, i.e. the local composition of the target is modified to a degree unattainable in common processes. A region of SiOx (x<2) - where x is a function of depth - is formed which is not stable. During annealing, the system relaxes towards equilibrium, i.e. phase separation (via spinodal decomposition and nucleation) sets in. Within a certain time window of annealing, the structure of the system matches with a structure similar to the multidot non-volatile memory device, the principal character of which is a 2D layer of Si nanoclusters of ~3nm in diameter which is embedded in a 3D SiO2 matrix at a distance of ~3nm from the Si substrate. The physical mechanisms of ion mixing of the two Si-SiOx interfaces and subsequent phase separation, which result in the desired sample structure, are elucidated from the viewpoint of computer simulation. In addition, experimental evidence is presented based on various methods, including TEM, RBS, and SIMS. Of particular importance is a novel method of Si nanocluster decoration which applies Ge as contrast enhancing element in TEM studies of tiny Si nanoclusters.

The current diverse and wide range of computing moves towards the cloud and de- mands high performance in low latency and high throughput. Facebook reported that 3.3 billion people monthly and 2.6 billion people daily use their data centers over the network. Many emerging user-facing applications require strict control over the stor- age latency’s tail to provide a quality user experience. The low-latency requirement triggers the ongoing replacement of hard drives (HDDs) by solid-state drives (SSDs) in the enterprise, enabling much higher performance and lower end-to-end storage latencies. It becomes more challenging to ensure low latency while maintaining the device’s endurance ratings. We address this challenge in the following ways: 1. Enhance the overall storage system’s performance and maintain the SSD endurance using emerging Non-volatile memory (ENVM) technology. 2. Implement deterministic la- tency in the storage path for latency-sensitive applications. 3. Provide low-latency and differentiated services when write-intensive workloads are present in a shared environment. We have proposed the performance and endurance-centric mechanisms to evaluate the tradeoffs between performance and endurance. In the first approach, our goal is to achieve low storage latency and a long lifetime of the SSD simultane- ously, even for a write-heavy workload. Incorporating a significantly smaller amount of ENVM with SSD as a cache helps to achieve the said goal.SSDs using the NVMe (Non-Volatile Memory Express) interface can achieve low latency as the interface provides several advanced features. The second approach has iii explored such features to control the storage tail latency in a distributed environment. The ”predictable latency mode (PLM)” advanced feature helps to achieve determinis- tic storage latency. SSDs need to perform many background management operations to deal with the underlying flash technology traits, the most time-consuming ones be- ing garbage collection and wear leveling. The latency requirement of latency-sensitive applications violates when the I/O requests fall behind such management activities. PLM leverages SSD controllers to perform the background operations during a win- dow, called a ”non-deterministic window (NDWin)”. Whereas during the ”determin- istic window (DTWin)”, applications will experience no such operations. We have extended this feature in the distributed environment and showed how it helps achieve low storage latency when the proposed ”PLM coordinator (PLMC)” is incorporated. In a shared environment with write-intensive workloads present, result in latency peak for Read IO. Moreover, it is required to provide differentiated services with multiple QoS classes present in the workload mixture. We have extended the PLM concept on hybrid storage to realize the deterministic latency for tight tail-controlled appli- cations and assure differentiated services among multiple QoS applications. Since nearly all of the storage access in a data center is over the network, an end-to-end path consists of three components: The host component, Network component, and Storage Component. For latency-sensitive applications, the overall tail latency needs to consider all these components. In a NAS (Network Attached Storage) architecture, it is worth studying the QoS class aware services present at the different components to provide an overall low request-response latency. Therefore, it helps future research to embrace the gaps that have not been considered yet. / Computer and Information Science

The current diverse and wide range of computing moves towards the cloud and de- mands high performance in low latency and high throughput. Facebook reported that 3.3 billion people monthly and 2.6 billion people daily use their data centers over the network. Many emerging user-facing applications require strict control over the stor- age latency’s tail to provide a quality user experience. The low-latency requirement triggers the ongoing replacement of hard drives (HDDs) by solid-state drives (SSDs) in the enterprise, enabling much higher performance and lower end-to-end storage latencies. It becomes more challenging to ensure low latency while maintaining the device’s endurance ratings. We address this challenge in the following ways: 1. Enhance the overall storage system’s performance and maintain the SSD endurance using emerging Non-volatile memory (ENVM) technology. 2. Implement deterministic la- tency in the storage path for latency-sensitive applications. 3. Provide low-latency and differentiated services when write-intensive workloads are present in a shared environment. We have proposed the performance and endurance-centric mechanisms to evaluate the tradeoffs between performance and endurance. In the first approach, our goal is to achieve low storage latency and a long lifetime of the SSD simultane- ously, even for a write-heavy workload. Incorporating a significantly smaller amount of ENVM with SSD as a cache helps to achieve the said goal.SSDs using the NVMe (Non-Volatile Memory Express) interface can achieve low latency as the interface provides several advanced features. The second approach has iii explored such features to control the storage tail latency in a distributed environment. The ”predictable latency mode (PLM)” advanced feature helps to achieve determinis- tic storage latency. SSDs need to perform many background management operations to deal with the underlying flash technology traits, the most time-consuming ones be- ing garbage collection and wear leveling. The latency requirement of latency-sensitive applications violates when the I/O requests fall behind such management activities. PLM leverages SSD controllers to perform the background operations during a win- dow, called a ”non-deterministic window (NDWin)”. Whereas during the ”determin- istic window (DTWin)”, applications will experience no such operations. We have extended this feature in the distributed environment and showed how it helps achieve low storage latency when the proposed ”PLM coordinator (PLMC)” is incorporated. In a shared environment with write-intensive workloads present, result in latency peak for Read IO. Moreover, it is required to provide differentiated services with multiple QoS classes present in the workload mixture. We have extended the PLM concept on hybrid storage to realize the deterministic latency for tight tail-controlled appli- cations and assure differentiated services among multiple QoS applications. Since nearly all of the storage access in a data center is over the network, an end-to-end path consists of three components: The host component, Network component, and Storage Component. For latency-sensitive applications, the overall tail latency needs to consider all these components. In a NAS (Network Attached Storage) architecture, it is worth studying the QoS class aware services present at the different components to provide an overall low request-response latency. Therefore, it helps future research to embrace the gaps that have not been considered yet. / Computer and Information Science

As the semiconductor industry grapples with escalating scaling challenges associated with the floating gate MOSFET, alternative memory technologies like Resistive Random Access Memory (ReRAM) are gaining prominence in the scientific community. Boasting a straightforward device structure, ease of fabrication, and compatibility with CMOS (Complementary Metal-oxide Semiconductor) Back-end of Line (BEOL), ReRAM stands as a leading candi- date for the next generation of non-volatile memory (NVM). ReRAM devices feature nanoionics-based filamentary switching, outperforming flash memory in terms of power consumption, scalability, retention, ON/OFF ratio, and endurance. Furthermore, integrating ReRAMs within the CMOS BEOL/low-k Cu interconnect system not only reduces latency between the connectivity constraints of logic and memory modules but also minimizes the chip footprint. However, investigations have revealed a significant concern surrounding ReRAMs—specifically, their electro-thermal reliability. This research provides evidence highlighting the critical influence of material properties, deposition effects, and thermal transport on the device's performance and reliability. Various material systems have undergone in this work scrutiny to comprehend the impact of intrinsic material properties such as thermal conductivity, specific heat capacity, thermal diffusivity, and deposition effects like surface roughness on the electroforming voltages of ReRAM devices. The reference device structure considered in this work is Cu/TaOx/Pt, which has been compared with alternative configurations involving metals like Ru and Co as potential substitutes for Pt. Additionally, a new vehicle has been introduced to quantify cell degradation resulting from thermal cross-talk in crossbar Resistive Random Access Memory (ReRAM) arrays. Furthermore, a novel methodology has been presented to predict cell degradation due to remote heating, taking into account the cell's location, the material properties of the device, and geometry of its electrodes. The experimental results presented in this study showcase filament rupture caused by remote heating, along with spontaneous filament restoration ensuing from the subsequent cooling of the ReRAM cell. / Doctor of Philosophy / As the demand for compact, high-speed logic-memory modules continues to surge, the diminishing silicon real estate in our gadgets poses a challenge in extending Moore's law to meet the scaling needs of the semiconductor device industry. To tackle this challenge, emerging memory technologies like Resistive Random Access Memory (ReRAM) are positioned as promising successors to flash memory. ReRAM devices offer distinct advantages over flash memory, showcasing superior power consumption, scalability, long retention, a high ON/OFF ratio, and good endurance. Their compatibility with current CMOS (Complementary Metal-oxide Semiconductor) technology facilitates seamless integration. However, a significant concern associated with ReRAMs is their electro-thermal reliability. This research delves into how material properties comprising a ReRAM device and fabrication factors, such as the surface roughness of the material, can impact the electrical and thermal reliability of a ReRAM cell. In this context, a novel methodology has been introduced to predict cell degradation within ReRAM crossbar arrays induced by thermal cross-talk, considering material properties and the geometry of the device. The new methodology has been thoroughly verified on manufactured ReRAM arrays with various composite electrodes. The study also presents experimental results demonstrating the rupture of cell filaments due to remote heating, along with instances of spontaneous filament restoration due to subsequent cooling.

While the scaling of conventional memories based on floating gate MOSFETs is getting increasingly difficult, novel type of non-volatile memories, such as resistive switching memories, have lately found increased attention by both industry and academia. Resistive switching memory (ReRAM) is being considered one of the prime candidates for next-generation non-volatile memory due to relatively high switching speed, superior scalability, low power consumption, good retention and simplicity of its structure which does not require the expensive real estate structure of the silicon substrate. Furthermore, integration of ReRAM directly into a CMOS low-k/Cu interconnect module would not only reduce latency in connectivity constrained devices, but also would reduce chip's footprint by stacking memory layers on top of the logic circuits. One good candidate is the well-behaved Cu/TaOx/Pt resistive switching device. However, since platinum (Pt) acting as the inert electrode is not an economic choice for industrial production, a Back End of Line (BEOL)-compatible replacement of Pt is highly desirable. A systematic investigation has been conducted and metals such as Ru, Rh and Ir are found to be the best potential candidates to supplant Pt. The device properties of Ru, Rh and Ir based resistive switching devices have been explored in this work. However, the challenges of implementing ReRAM cell into BEOL of CMOS encompass not only the choice of materials of a CBRAM cell proper, but also the way the cell is embedded within BEOL. In case of the inert electrode, the metal interfacing the solid electrolyte (e.g. TaOx) has to be supplanted by a glue layer, and heat transport layer, leading to an engineering task of a composite electrode beyond the requirements of low miscibility with, and low surface diffusivity of the inert electrode with respect of the active metal atoms released by the active electrode (here Cu). The metal of the active electrode (Cu, Ag, Ni) is required to allow for a copious redox reaction but simultaneously preventing reactions with the dielectric. Finally, for the solid electrolyte, a dielectric with a moderate level of defects is preferred which may be controlled, for example by the deposition processes modulating the stoichiometry of the material. This research study begins with exploration of several devices derived from the benchmark device Cu/TaOx/Pt and manufacturing those in Micron nanofabrication and characterization laboratory at Virginia Tech with the latter device used as a benchmark for performance assessment. Electric characterization of the manufactured Cu/TaOx/Ru devices has shown some notable differences between them due to the different formation, shape and rupture of the conductive filament. The inferior switching properties of the Ru device have been attributed to the substantially degraded inertness properties of the Ru electrode as a stopping barrier for Cu as compared to the Pt electrode. To study this degradation effect further, two nominally identical devices however differently embedded on the Si wafer have been fabricated. The electric behavior of the two devices are found to be markedly different and is attributed to the difference in high local temperatures in the device during the switching that cause species interlayer diffusion and trigger undesired chemical reactions. Thus, the embedment of the device has a foremost impact on the intrinsic device performance. To investigate the impact of inert electrode on the endurance of ReRAM memory cells, baseline device Cu/TaOx/Pt/Ti is compared with six devices manufactured with different inert electrode constructions: Pt/Cr, Rh/Cr, Rh/Ti, Rh/Al2O3, Ir/Ti, and Ir/Cr, while the Cu electrode and the TaOx dielectric are identical. Although the glue layers Ti, Cr or Al2O3 are not an inherent part of the device proper, they have a tangible impact on the device endurance as well. It is experimentally demonstrated that inert electrodes with high thermal conductivities have superior endurance properties over an electrode with low thermal conductivity and the heat conductivity of inert electrode has a substantial impact on ReRAM cell performance. Since reset operation is a thermally driven process, frequent switching of resistive memory cell leads to a local accumulation of Joules heat, especially when the switching rate is faster than the heat removal rate. This investigation of local heating effects led to the exploration of non-local heat transfer within a memory array. In a crossbar arranged ReRAM cell array, heat generated in one device spreads via common electrode metal lines to the neighboring cells causing their performance degradation constituting non-local heat transfer mechanism leading to performance deterioration of neighboring cells. In addition to the electrical characterization of devices affected by the remote heat transfer, novel cell array architectures have been proposed and investigated with the goal to significantly mitigate the cell-to-cell thermal crosstalk. One of the possible mitigation measures would be modified cell erasure algorithm. / Doctor of Philosophy / Emerging memory technologies are being intensively investigated for extending Moore's scaling law in the next decade. The resistive random-access memory (ReRAM) is one of the most propitious contenders to replace the current ubiquitous FLASH memory. ReRAM shows unique nanoionics based filamentary switching mechanism. Compared to the current nonvolatile memory based on floating gate MOSFET transistor, the advantages of ReRAM include superior scalability, low power consumption, high OFF-/ON-state resistance ratio, excellent endurance, and long retention of the logic bit states. Besides the nonvolatile memory applications, resistive switching devices implement the function of a memristor which is the fourth basic electrical component and can be used for neuromorphic computing. A ReRAM device is in essence a metal-insulator-metal structure. One of the metal electrodes is called the active electrode and provides the building material for the filamentary connection between the electrodes. An important requirement of the second electrode, called the inert electrode, is to be immiscible with the metal atoms of the active electrode and to exhibit a minimum of susceptibility to structural changes and chemical reactions. This research presents a thorough investigation of the role and properties of the inert electrode and offers guideline for the optimal selection of the inert electrode in a commercially viable product. It has been found out that one important property of the inert electrode is its heat conductivity and also the way the inert electrode is embedded on a substrate. Consequently, the concept of the inert electrode has been replaced by the concept of engineered inert electrode module which evolved from a single metal layer to a multilayer stack displaying glue layers, high thermal conductivity layers dissipating the heat quickly, and diffusion stop layers eliminating unwanted chemical reactions. The investigation of the electro-thermal effects led to the discovery of the cell-to-cell thermal cross talk within the memory array which can seriously affect the performance of cells impacted by the remote heat transfer. When a memory cell is switched repeatedly a considerable amount of heat is dissipated in the cell and the heat may spread to neighboring cells that share the same metal lines. This heat transfer causes degradation of electrical performance of the neighboring cells. A method has been developed to characterize quantitatively how the electrical performance is affected by the thermal cross-talk impacting the electric performance of neighboring cells. Several novel mitigation strategies of new memory array architectures have been proposed and investigated.

Owing to its excellent scaling potential, low power consumption, high switching speed, and good retention, and endurance properties, Resistive Random Access Memory (RRAM) is one of the prime candidates to supplant current Nonvolatile Memory (NVM) based on the floating gate (FG) MOSFET transistor, which is at the end of its scaling capability. The RRAM technology comprises two subcategories: 1) the resistive phase change memory (PCM), which has been very recently deployed commercially, and 2) the filamentary conductive bridge RAM (CBRAM) which holds the promise of even better scaling potential, less power consumption, and faster access times. This thesis focuses on several aspects of the CBRAM technology. CBRAM devices are based on nanoionics transport and chemo-physical reactions to create filamentary conductive paths across a dielectric sandwiched between two metal electrodes. These nano-size filaments can be formed and ruptured reliably and repeatedly by application of appropriate voltages. Although, there exists a large body of literature on this topic, many aspects of the CBRAM mechanisms and are still poorly understood. In the next paragraph, the aspects of CBRAM studied in this thesis are spelled out in more detail. CBRAM cell is not only an attractive candidate for a memory cell but is also a good implementation of a new circuit element, called memristor, as postulated by Leon Chua. Basically, a memristor, is a resistor with a memory. Such an element holds the promise to mimic neurological switching of neuron and synapses in human brain that are much more efficient than the Neuman computer architecture with its current CMOS logic technology. A memristive circuitry can possibly lead to much more powerful neural computers in the future. In the course of the research undertaken in this thesis, many memristive properties of the resistive cells have been found and used in models to describe the behavior of the resistive switching devices. The research performed in this study has also an immediate commercial application. Currently, the semiconductor industry is faced with so-called latency scaling dilemma. In the past, the bottleneck for the signal propagation was the time delay of the transistor. Today, the transistors became so fast that the bottleneck for the signal propagation is now the RC time delay of the interconnecting metal lines. Scaling drives both, resistance and parasitic capacitance of the metal lines to very high values. In this context, one observes that resistive switching memory does not require a Si substrate. It is therefore an excellent candidate for its implementation as an o n-chip memory above the logic circuits in the CMOS back-end, thus making the signal paths between logic and memory extremely short. In the framework of a Semiconductor Research Corporation (SRC) project with Intel Corporation, this thesis investigated the breakdown and resistive switching properties of currently deployed low k interlayer dielectrics to understand the mechanisms and potential of different material choices for a realization of an RRAM memory to be implemented in the back-end of a CMOS process flow. / Master of Science

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