The conventional floating gate NVSM will suffer some limitations for continued scaling of the device structure. The floating gate is a continuous semiconductor thin film which charges are stored in and able to move around. With the scaling of tunneling oxide, the thickness is decreased gradually. Once the tunneling oxide has been created a leaky path, all the stored charges in the FG will be lost after numerous counts of write/erase operation. When the tunnel oxide is thinner, the phenomenon happens more easily but the speed of write/erase operation is quicker. Therefore, there is a tradeoff between speed and reliability.Therefore, two approaches, the silicon-oxide-nitride-oxide-silicon (SONOS) and the nanocrystal nonvolatile memory devices, have been investigated to overcome the limit of the conventional floating gate NVSM. In this thesis, the nonvolatile nanocrystal memory structures were proposed for electrical analysis and physical mechanism studied. We proposed two nanocrystal memory, silicon nanocrystal memory and nickel-silicide nanocrystal memory. The silicon nanocrystal memories have standard sample and nitridation sample. The interface between the nitride and Si-dots can offer extra trap cites for electrons storage. And the nickel-silicide dots memory has standard sample and high-k sample. The HfO2 layer for control oxide can increase the electric field of the tunnel oxide to get better programming efficiency.

Recently, many kinds of memory devices had been discussed, such as static random access memory (SRAM), dynamic random access memory (DRAM), the flash memory, ferroelectric random access memory (FRAM), magnetron random access memory (MRAM) and etc. In the volatile and nonvolatile memories, the non-destructive readout feature of high density nonvolatile memories will play an important role in the future. The structure characteristics of nonvolatile FeRAM with non-destructive metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFM) structures would be discussed in this study. Among many ferroelectric materials, such as pervoskite (ABO3) and bi-layer ferroelectric (BLFS) structures had been widely investigated and discussed for applications in non-volatile ferroelectric random access memory devices. However, the ferroelectric materials such as (Ba,Sr)TiO3 and Ba(Ti,Zr)O3 thin films were expected to substitute the PZT or SBT memory materials and improve the environmental pollution because of their lower pollution problem. According to system on panel (SOP) concept, the switch characteristics of various thin-film transistors had been widely investigated for the amorphous silicon (a-Si) and poly-crystaline silicon (poly-Si) active matrix LCD (AM-LCD) display applications. Therefore, the integrated electronic devices such as memory device, control device, central processing unit (CPU) and etc will be important research and study in the future. According the statement, we would investigate that the ferroelectric Ba(Zr0.1Ti0.9)O3 (BZT) composition could be used in a one-transistor-capacitor (1TC) structure of the amorphous-Si TFT device to replace the gate oxide of random access memory devices. In this study, the rf magnetron sputtering was used to deposit BZT ferroelectric thin films on Pt/Ti/SiO2/Si and ITO/glass substrates, and MFM and MFIS structures were also fabricated. The effects of various sputtering parameters on the physical and electrical characteristics of BZT thin films such as the oxygen concentrations, rf power, substrate temperature, chamber pressure and deposition time were discussed. From the XRD, AFM and SEM analysis, the various peaks, surface roughness, grain size and thickness of as-deposited BZT thin film were also found. From the C-V and J-E curves of MFM and MFIS structures, the maximum capacitance, dielectric constant, memory window and leakage current density were obtained. After rapid thermal annealing (RTA), the capacitances, remanent polarization (P-E) curves and leakage current density of MFM structure in Pt/Ti/SiO2/Si and ITO/glass substrates were improved. In addition, we found that the higher capacitance, larger memory windows and lower leakage current density of BTV/BZT dual layer structure using annealed BZT films would be increased in this study. Finally, the one-transistor-capacitor (1TC) structure of ferroelectric random access memory (FeRAM) with the gate oxide of BZT thin films on the amorphous silicon TFT structure have been fabricated and investigated. The Ion/Ioff drain current ratio, drain current window, ID-VG, ID-VD curves, threshold voltage (VT) and subthreshold swing (SS) properties of 1TC bottom-gated FeRAM device were obtained under the linear and saturation region. From the results in this study, the BZT thin films for bottom-gated amorphous thin-film transistor will be a suitable candidate to fabricate with ferroelectric random access memory (FeRAM) devices for system on panel (SOP) applications.

In a conventional nonvolatile memory, charge is stored in a polysilicon floating gate (FG) surrounded by dielectrics. The scaling limitation stems from the requirement of very thin tunnel oxide layer. For FG, once the tunnel oxide develops a leaky path under repeated write/erase operation, all the stored charge will be lost.Therefore, the thickness of the tunnel oxide can not be scaled down to about 7 nm. To alleviate the scaling limitation of the conventional FG device while preserving the fundamental operating principle of the memory, we have studied the distributed charge storage approach such as the nanocrystal nonvolatile memory. Each nanodot will typically store only a handful of electrons; collectively the charges stored in these dots control the channel conductivity of the memory device. Nanocrystal charge storage offers several advantages, the main one being the potential to use thinner tunnel oxide without sacrificing non-volatility. This is a quite attractive proposition since reducing the tunnel oxide thickness is a key to lowering operating voltages and/or increasing operating speeds. The improved scalability results not only from the distributed nature of the charge storage, which makes the storage more robust and fault-tolerant, but also from the beneficial effects of Coulomb blockade. A local leaky path will not cause a fatal loss of information for the nanocrystal non-volatile memory device. Also, the nanocrystal memory device can maintain good retention characteristics and lower the power consumption. In recent years, nonvolatile memory with nanocrystals cell have widely applied to overcome the issue of operation and reliability for conventional floating gate memory. The excellent electrical characteristics of memory device need good endurance, long retention time and small operation voltage. Among numerous memory devices with nanocrystals, the memory device with metal nanocrystals was widely researched. It will be a new candidate for flash memory. The advantages of metal nanocrystals has have higher density of states around Fermi level, stronger coupling with conduction channel, wide range of available work functions and smaller energy perturbation due to carrier confinement. So metal nanocrystals can reduce operate voltage, and increase write/erase speed and endurance. Most important of all, we can control the sizes of nanocrystals dot and manufacture at low temperature¡CThis advantage can apply to thin film transistor liquid crystal display; it fabricates driving IC and logical IC on panel for diverseness and adds memory beside switch TFT as image storage to reduce power consumption for portability. In this thesis, we will discuss metal nanocrystals as memory storage medium. And we can use high temperature oxidation, low temperature annealing with oxygen to form nanocrystals. Most importantly, we analyze the effect of electron storage at metal nanocrystals by means of material and electrical analysis.

Current requirement of nonvolatile memory (NVM) are high density cell, low-power wastage, high speed operation, and good reliability for the scaling down device. In a conventional nonvolatile memory, once the tunnel oxide develops a leaky path under repeated write/erase operation, all the stored charge will be lost. Therefore, the tunnel oxide thickness is incapable to scale down in terms of charge retention and endurance characteristics. Therefore conventional floating gate (FG) nonvolatile memories (NVMs) present critical issues on device scalability beyond the sub-50nm node. The nonvolatile nanocrystal memories are one of promising candidates to substitute for the conventional floating gate (FG) memories, because the nanocrystal memories storage charge by separated node. So it is not major influence of charge lost from partial oxide layer. The thickness of tunnel oxide can be reduce also can maintain good retention, therefore it is key to lowering operating voltages and increasing operating speeds. Also reduce device to increasing the density of device. The advantages of metal nano-dot compared with other material counterparts include stronger coupling with the conduction channel, a wide range of available work functions, and higher density of states around the Fermi level. Because these advantages. It is possibility of metal nanocrystals nonvolatile memory fabricated in industry in practice. In this thesis, an ease and low temperature fabrication technique of Co-Si-N nanocrystals was demonstrated for the application of nonvolatile memory. The nonvolatile memory structure of Co-Si-N nanocrystals embedded in the SiOx layer was fabricated by sputtering a co-mix target (CoSi2) in an Ar/N2 environment at room temperature. It can be considered that the nitrogen plays a critical role during sputter process for the formation of nanocrystal. In addition, the high density (~1012 cm-2) nanocrystal can be simple and uniform to be fabricated in our study. We also proposed a formation of Co-Si-N nanocrystals by sputtering a co-mix target (CoSi2) in the Ar/NH3 environment at room temperature. It was also found that high density Ni-Si-N nanocrystals embedded in the silicon nitride (SiNx) and larger memory effect. A rapid thermal annealing (RTA) with process temperature at 700¢XC¡B800¢XC and short duration (60sec) was used to form nanocrystals. The charge storage layer of nanorystals embedded in SiNx shows larger memory window and better reliability over nanocrystals embedded in SiOx, due to different distributions of electronic field .

The conventional floating gate NVSM will suffer some limitations for continued scaling of the device structure. Therefore, the silicon-oxide-nitride-oxide-silicon (SONOS) and the nanocrystal nonvolatile memory devices, have been investigated to overcome the limit of the conventional floating gate NVSM. For driving device application, we have used multilayer ONO gate dielectrics to make change the effective dielectric constant. The proposed TFT with ONO gate dielectrics have better gate control ability. On the other hand, nanowire has larger electric-field in the corner region at the same voltage. The SONOS-TFT with multiple nanowire channels have superior electrical characteristic, such as lower threshold voltage, higher On/Off ratio, steeper subthreshold slope, and superior driving ability. The memory characteristic of standard SONOS-TFT, channel width of the device is 1£gm, was compared with the nanowires SONOS-TFT, each channel width of the device is 65nm. The SONOS-TFT with multiple nanowires structure (NW SONOS-TFT) has good program/erase efficiency, retention, transfer characteristics and can suppress gate injection effectively. These characteristics are due to the larger electric field at the corner region and more number of corners. The NW SONOS-TFTs can be treated as high performance devices and also as high program/erase efficiency nonvolatile memory under adequate voltage range operation. In this thesis, the P/E characteristics at different temperatures will also be measured and discussed. The fabrication of SONOS-TFTs with nano-wire channels is quite easy and involves no additional processes. Such a SONOS-TFT is there by highly promising for application in the future system-on-panel display applications. The SONOS-TFTs combined the TFT and memory properties at the same time. Furthermore, the process flow is compatible with conventional poly-Si TFTs fabrication without additional process steps. Hence, the application of SONOS TFTs structure can reach the goal of system on panel (SOP) in the future.

No description available.

Nanocrystals embedded zirconium-doped hafnium oxide (ZrHfO) high-k gate dielectric films have been studied for the applications of the future metal oxide semiconductor field effect transistor (MOSFET) and nonvolatile memory. ZrHfO has excellent gate dielectric properties and can be prepared into MOS structure with a low equivalent oxide thickness (EOT). Ruthenium (Ru) modification effects on the ZrHfO high-k MOS capacitor have been investigated. The bulk and interfacial properties changed with the inclusion of Ru nanoparticles. The permittivity of the ZrHfO film was increased while the energy depth of traps involved in the current transport was lowered. However, the barrier height of titanium nitride (TiN)/ZrHfO was not affected by the Ru nanoparticles. These results can be important to the novel metal gate/high-k/Si MOS structure. The Ru-modified ZrHfO gate dielectric film showed a large breakdown voltage and a long lifetime. The conventional polycrystalline Si (poly-Si) charge trapping layer can be replaced by the novel floating gate structure composed of discrete nanodots embedded in the high-k film. By replacing the SiO2 layer with the ZrHfO film, promising memory functions, e.g., low programming voltage and long charge retention time, can be expected. In this study, the ZrHfO high-k MOS capacitors that separately contain nanocrystalline ruthenium oxide (nc-RuO), indium tin oxide (nc-ITO), and zinc oxide (nc-ZnO) have been successfully fabricated by the sputtering deposition method followed with the rapid thermal annealing process. Material and electrical properties of these kinds of memory devices have been investigated using analysis tools such as XPS, XRD, and HRTEM; electrical characterizations such as C-V, J-V, CVS, and frequency-dependent measurements. All capacitors showed an obvious memory window contributed by the charge trapping effect. The formation of the interface at the nc-RuO/ZrHfO and nc-ITO/ZrHfO contact regions was confirmed by the XPS spectra. Charges were deeply trapped to the bulk nanocrystal sites. However, a portion of holes were loosely trapped at the nanocrystal/ZrHfO interface. Charges trapped to the different sites lead to different detrapping characteristics. For further improving the memory functions, the dual-layer nc-ITO and -ZnO embedded ZrHfO gate dielectric stacks have been fabricated. The dual-layer embedded structure contains two vertically-separated nanocrystal layers with a higher density than the single-layer embedded structure. The critical memory functions, e.g., memory window, programming efficiency, and charge retention can be improved by using the dual-layer nanocrystals embedded floating gate structure. This kind of gate dielectric stack is vital for the next-generation nonvolatile memory applications.

Resistive Random Access Memory (RRAM) is considered as the most promising candidate for the next-generation nonvolatile memories due to their superior properties such as low operation voltage, fast operation speed, non-destructive read, simple metal-insulator-metal (MIM) sandwich structure, good scale-down ability. The main targets of this research are to clarify the corresponding physical mechanism, develop the potential material and structure of RRAM and stabilize the resistive switching characteristics, in which clarifying the physical mechanism will be the key factor for RRAM into production in the future. Recent research has suggested that variation of the low and high resistance states in RRAM could be caused due to the by instability in the formation and /disruption of the filament. In addition, the endurance and stability of RRAM may be related to the dissipation of oxygen ions in the switching layer. In this study, new material (Si Introduced) and structure (oxygen confined layer) are employed to improve RRAM performance and to clarify the physical mechanism. Furthermore, constant switching energy results can be used to select the optimal materials and structures also can be used to correctly allocate voltage and time to control RRAM. The detail physical mechanism is studied by the stable RRAM device (Ti/HfO2/TiN) which is offered from Industrial Technology Research Institute (ITRI). The switching process is proved as the formation/disruption of the filament. Furthermore, the dynamic switching behaviors during reset procedure in RRAM were analyzed by the sequential experimental design to illustrate the procedure of atomic quantized reaction at the ultra-cryogenic temperature.

In a conventional nonvolatile memory (NVM), charge is stored in a ploy-silicon floating gate (FG) surrounded by dielectrics. But, it will suffer some limitations for continued scaling of the device structure. Therefore, the nanocrystal nonvolatile memory devices have been investigated to overcome the limit of the conventional floating gate NVM in recently years. Nanocrystal charge storage offers several advantages, the main one being the potential to use thinner tunnel oxide without sacrificing nonvolatility. This is a quite attractive proposition since reducing the tunnel oxide thickness is a key to lowering operating voltage and/or increasing operating speeds. In this thesis, we have fabricated tungsten (W) nanocrystals nonvolatile memory devices. A thin tungsten silicide (W5Si3) layer was deposited on tunnel oxide layer first. The following oxidation was performed in furnace system. The W element tends to segregate downward and precipitate on the tunnel oxide after thermal oxidation. In addition, the silicon element is oxidized into silicon dioxide surrounded tungsten nanocrystals. Also, the carrier gas, such as O2 and N2, were also added as the tungsten silicide deposition. The memory effect and the electrical reliability for W nanocrystals surrounded in different dielectric were also investigated in this study. In addition, the formation mechanism of W nanocrystals with additional silicon oxide capped on tungsten silicide was also investigated. The thicker silicon oxide can effectively control the thermal oxidation condition and prevent thin film degradation. However, the overall oxidation cause the memory window reduction and the electrical characteristics degradation, resulted from the partially oxidation of W nanocrystal to metal-incorporated dielectric. By contrast, we also demonstrated the structure that deposited the charge trapping layer by co-sputtered W and dielectric material as SiO2 or Si3N4 to directly form the W nanocrystal embedded in dielectrics. Besides, the W and Si directly deposited by co-sputtered to adjust the two elements contained ratio had investigated as well in this study. Furthermore, the memory effect and electrical characteristics for germanium (Ge) element incorporated W nanocrystal memory were also discussed. The additional storage element contributes the memory effect. In summary, the memory effect for W nanaocrystal embedded in different dielectric, the effect of the thermal treatment for additional silicon oxide incorporation, and the contribution of the Ge element to the memory effect can be obtained from the fabrication of W nanocrystal memory were finished in this study.

Current requirements of nonvolatile memory (NVM) are the high density cells, low-power consumption, high-speed operation and good reliability for the scaling down devices. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVMs. Therefore, the tunnel oxide thickness is difficult to scale down in terms of charge retention and endurance. The nanocrystal nonvolatile memories are one of promising substitution, because the discrete storage nodes as the charge storage media have been effectively improve data retention under endurance test for the scaling down device. Many methods have been developed recently for the formation of nanocrystals. Generally, most methods need thermal treatment with high temperature and long duration. This procedure will influence thermal budget and throughput in current manufacture technology of semiconductor industry. And supercritical carbon dioxide (SCCO2) has been researched to the passivation of dielectric and reducing the activation energy. The research estimates SCCO2 is potential to form nanocrystals for these reason. This research is to discuss the feasibility of fabricating nanocrystal NVMs device with low temperature SCCO2. The low melting point metal material Sn is used for the attempts. In order to check if Sn can be used for fabricating nanocrystal NVMs device, the research selects the conventional thermal annealing method first. It uses rapid thermal annealing to improve the crystalline of nanocrystals and reliability of the memory device. Compare to different Sn containment or chemistry and different process, analyze the electric characteristics and materials chemistry. At last, select the Sn and SiO2 co-sputtering film to try the SCCO2 process and analyze these characteristics as well. Due to the novel technology, many physical mechanism and improvement of properties will be discuss following.