The development of digital technology permits the storage and processing of binary data at high rates, with high precision and density. Therefore, over the past few decades, Moore's law has pushed the development of scaling semiconductor devices for computing hardware. Although the current downward scaling trend has reached its scaling limits, a new "More-than-Moore" (MtM) trend has been emphasized as a diversified function of data collection, storage units, and processing devices. The function diversification defined in MtM can be viewed as an alternative form of "scaling down" for electronic systems, as it incorporates non-computing functions into digital ones, allowing digital devices to interact directly with the environment around them. Two-dimensional (2D) materials display promising potential for combining optical sensing and data storage with broadband photoresponse, outstanding photoresponsivity, rapid switching speed, multi-bit data storage, and high energy efficiency. In this work, in-solution 2D materials flakes (Hafnium Diselenide (HfSe2) and Germanium Selenide (GeSe) have been studied as a charge-trapping layer in non-volatile memory through the seamless fabrication process. Furthermore, the behavior of fabricated non-volatile memories under light illumination has been investigated towards in-memory light sensing. Atomic Force Microscopy, RAMAN spectroscopy, and X-ray Diffraction Spectroscopy characterized the charge-trapping materials. The electrical characterization of Metal Oxide Semiconductor (MOS) Capacitor memory revealed a memory window of 4V for the HfSe2 device under ±10V biasing. Intriguingly, the GeSe device exhibited an extraordinarily wide memory window of 11V under the same electrical biasing. Furthermore, the memory endurance for both materials as charge trapping layer (CTL) exceeds the standard threshold of electrical programming and erasing cycles. The accelerated retention test at different temperatures showed the memory device's stability and reliability for both materials. Under light stimuli with electrical readout voltage, the MOS memory exhibited wavelength and intensity-responsive behavior. The MOS memory of HfSe2 has demonstrated remarkable capabilities in storing the detected light signal, while also exhibiting a noteworthy increase in the memory window of approximately 1.8 V when subjected to a laser wavelength of 405 nm. Meanwhile, the GeSe device's CV measurement revealed a similar trend with the greatest memory window enhancements occurring in relation to 465 nm laser wavelength. Under ±6 V biasing in the absence of light, the memory window was found to be 8.3 V. However, following exposure to a 465 nm laser, this value increased significantly to 9.9 V, representing an increment of 1.6 V. In addition, both devices exhibited distinct sensing of various light intensities and an enhanced memory window as a result of the observable Vt shift caused by altering the levels of illumination. This memory enhancement suggests that photoexcited carriers in the CTL layer were responsible for the optical memory behavior. The 2D materials as CTL pave the way for a reconfigurable optical memory with multilevel optical data storage capacity. This research represents a significant step towards the development of a new generation of memory devices that can store and retrieve data using light signals.

Emerging memory technologies are being intensively investigated for extending Moore\'s law in the next decade. The conductive bridge random access memory (CBRAM) is one of the most promising candidates. CBRAM shows unique nanoionics-based filamentary switching mechanism. Compared to flash memory, the advantages of CBRAM include excellent scalability, low power consumption, high OFF-/ON-state resistance ratio, good endurance, and long retention. Besides the nonvolatile memory applications, resistive switching devices implement the function of memristor which is the fourth basic electrical component. This research presents the characterization and modeling of Cu/TaOx/Pt resistive switching devices. Both Cu and oxygen vacancy nanofilaments can conduct current according to the polarity of bias voltage. The volatile resistive switching phenomenon has been observed on Cu/TaOx/delta-Cu/Pt devices and explained by a flux balancing model. The resistive devices are also connected in series and in anti-parallel manner. These circuit elements are tested for chaotic neural circuit. The quantum conduction has been observed in the I-V characteristics of devices, evidencing the metallic contact between the nanofilament and electrodes. The model of filament radial growth has been developed to explain the transient I-V relation and multilevel switching in the metallic contact regime. The electroforming/SET and RESET processes have been simulated according to the mechanism of conductive filament formation and rupture and validated by experimental results. The Joule and Thomson heating effects have also been investigated for the RESET processes. / Ph. D.

Resistive random access memory (RRAM), based on a two-terminal resistive switching device with a switching element sandwiched between two electrodes, has been an attractive candidate to replace flash memory owing to its simple structure, excellent scaling potential, low power consumption, high switching speed, and good retention and endurance properties. However, due to the current limited understanding of the device mechanism, RRAMs research are still facing several issues and challenges including instability of operation parameters, the relatively high reset current, the limited retention and the unsatisfactory endurance. In this study, we investigated the switching mechanisms, conditions and applications of oxygen vacancy (Vo) filament formation in resistive memories. By studying the behavior of conductive Vo nanofilaments in several metal/oxide/metal resistive devices of various thicknesses of oxides, a resulting model supported by the data postulates that there are two distinct modes of creating oxygen vacancies: i) a conventional bulk mode creation, and ii) surface mode of creating oxygen vacancies at the active metal-dielectric interface. A further investigation of conduction mechanism for the Vo CF only based memories is conducted through insertion of a thin layer of titanium into a Pt/ Ta2O5/Pt structure to form a Pt/Ti/ Ta2O5/Pt device. A space charge limited (SCL) conduction model is used to explain the experimental data regarding SET process at low voltage ranges. The evidence for existence of composite copper/oxygen vacancy nanofilaments is presented. The innovative use of hybrid Vo/Cu nanofilament will potentially overcome high forming voltage and gas accumulation issues. A resistive floating electrode device (RFED) is designed to allow the generation of current/voltage pulses that can be controlled by three independent technology parameters. Our recent research has demonstrated that in a Cu/TaOx/Pt resistive device multiple Cu conductive nanofilaments can be formed and ruptured successively. Near the end of the study, quantized and partial quantized conductance is observed at room temperature in metal-insulator-metal structures with graphene submicron-sized nanoplatelets embedded in a 3-hexylthiophene (P3HT) polymer layer. As an organic memory, the device exhibits reliable memory operation with an ON/OFF ratio of more than 10. / Ph. D.

Recently, active matrix flat-panel displays are widely used in consumer electronic products. With increasing popularity of flat-panel displays, market competition becomes more intense and demands for high performance flat-panel displays are increasing. Low-temperature polysilicon (LTPS) with higher mobility, as well as drive current can integrate electric circuit, such as controllers and memory on glass substrate of display to achieve the purpose of system on panel (SOP). Thus, flat-panel displays can be more compact, while reducing reliability issues and lowering production costs. In this dissertation, we studied the nonvolatile memory for system on panel applications and reducing cost of memory by increasing the memory density or reducing the processing steps. Therefore, we proposed several modes of operation in nonvolatile memory. First, we use channel hot-electron (CHE) to inject electrons into the nitride layer that¡¦s above source or drain sides of SONOS thin film transistor (TFT). Thus, we can increase the memory density by storing two-bit state in a memory cell. In this study, the two-bit memory effect is clearly observed for devices with a shorter gate length after CHE programming; however, the two-bit memory effect is absent in devices with a longer gate length. The gate-length-dependent two-bit memory effect is related to the location of injected electrons in the nitride layer. When electrons are injected into the nitride layer above the channel, they can create an additional energy barrier in the channel thus increasing the threshold voltage of the device to perform the programming operations. However, if electrons are injected into the depletion region at the P-N junction between the drain and the channel, the energy barrier induced by electrons is not significant when exchanging the source and drain electrodes to measure the memory status, and the program effect is not as significant. When the channel length is shorten, the built-in potential between the source and the channel can be decreased, the energy barrier caused by programmed electrons can affect electrons in the channel and increase the threshold voltage. Therefore, the two-bit memory effect can be seen in devices with the shorter gate length after CHE programming. Secondly, we stored charges in the body of the thin film transistor to make the conventional thin-film transistors become a non-volatile memory. This method does not need a floating gate or a tunneling oxide in the memory cell; therefore the memory cost can be reduced. In this study, we used trap-assisted band-to-band thermionic field emission enhanced by self-heating in TFT to produce electron-hole pairs. The hole will be separated by a vertical field under the gate and be injected into the body of TFT to complete the programming operation. The erasing operation is performed by applying a lateral electric field between the source/drain to remove holes in the body of TFT. Thirdly, we proposed an edge-FN tunneling method to allow SONOS TFT possess not only a pixel switch but also a two-bit nonvolatile memory function in a display panel, thus causing the memory density to increase. In this study, we used a channel FN tunneling to program the SONOS TFT. Because the electric field in the gate-to-drain overlap region is larger than that in the channel region, it will cause a smoother electron injection into the nitride layer inside of the gate-to-drain overlap region, which also increases the gate-induced drain leakage (GIDL) current. The edge-FN tunneling method is used to erase electrons in the gate-to-drain overlap region, by doing so, the GIDL current has decreased. The memory status at the source/drain side is determined by the corresponding GIDL current of the SONOS TFT. Fourthly, we stored electrons in the nitride layer at source, channel, and drain regions of SONOS TFT to make sure that TFT possess a three-bit memory effect in a unitary cell, which also allows the memory density to increase significantly. In this study, programming and erasing operations in the source/drain region are performed by channel hot-electron injection and edge-FN tunneling method, while that in the channel region are accomplished by channel FN tunneling. The memory status in the source/drain is determined by the corresponding GIDL current, while that in the channel region by threshold voltage of the device The memory density for the device operated by proposed method can be further increased. In addition, if we store a number of N different types of electrons in those three regions mentioned above, there are N3 status can be stored in a memory cell. The memory density can beyond conventional multi-level-cell (MLC) flash memory. Two-bit memory effect per cell in a MLC flash memory can be achieved by storing four quantitative electrons in the floating gate of the memory device. If we store four quantitative electrons in the nitride layer at source, channel, and drain regions of SONOS TFT, we can obtain 64 memory states or 6-bit memory effect in a memory cell. Thus, the proposed concept is promising to storage the messages in a memory cell beyond four-bit.

Logic-in-memory circuits promise to overcome the von-Neumann bottleneck, which constitutes one of the limiting factors to data throughput and power consumption of electronic devices. In the following we present four-input logic gates based on only two ferroelectric FETs (FeFETs) with hafnium oxide as the ferroelectric material. By utilizing two complementary inputs, a XOR and a XNOR gate are created. The use of only two FeFETs results in a compact and nonvolatile design. This realization, moreover, directly couples the memory and logic function of the FeFET. The feasibility of the proposed structures is revealed by electrical measurements of HKMG FeFET memory arrays manufactured in 28nm technology.

During the last decade ferroelectrics based on doped hafnium oxide emerged as promising candidates for realization of ultra-low-power non-volatile memories. Two spontaneous polarization states occurring in the material that can be altered by applying electrical fields rather than forcing a current through and the materials compatibility to CMOS processing are the main benefits setting the concept apart from other emerging memories. 1T1C ferroelectric random access memories (FeRAM) as well as 1T FeFET concepts are under investigation. In this article the application of hafnium based ferroelectric memories in different flavours and their ranking in the memory landscape are discussed.

La mémoire Flash est actuellement extrêmement utilisée en tant que mémoire non volatile pour le stockage des données numériques dans presque tout type d'appareil électronique nomade (ordinateur portable, téléphone mobile, tablette, …). Pour dépasser ses limites actuelles (densité d'informations, endurance, rapidité), un grand nombre de recherches se développent notamment autour du concept de mémoires résistives qui repose sur la commutation entre différents niveaux de résistance, via l'application d'une tension.Les mémoires dont la variation de résistance dépend de réactions électrochimiques (ReRAM) sont potentiellement de bonnes candidates pour les mémoires non volatiles de prochaine génération; les mécanismes d'oxydo-réduction impliqués sont cependant souvent de type filamentaire, mettant notamment en jeu des migrations de cations d’éléments métalliques (provenant des électrodes), ou de lacunes d’oxygène. Ce caractère filamentaire rend difficilement atteignable la miniaturisation extrême, à l’échelle nanométrique.Dans cette thèse, une classe de matériaux particulière -utilisée dans le domaine du stockage d'énergie- est étudiée. L’objectif est d’approfondir l’origine des processus de commutation de résistance observés sur des films de LixCoO2. Nous caractérisons d'abord les propriétés structurales et électriques de tels films, ainsi que le comportement électrique des dispositifs élaborés à partir de ces films. Nous étudions ensuite les mécanismes électrochimiques qui sont à l’origine des commutations résistives, dans la configuration d’un contact micrométrique électrode/film/électrode. Nous cherchons à déterminer la validité d’un mécanisme qui avait été proposé auparavant, mais non démontré. Nous étudions également la cinétique de commutation des dispositifs, et proposons un modèle numérique permettant d’expliquer les résultats expérimentaux observés. Enfin, nous étudions l’applicabilité potentielle des dispositifs (intégrant les films de LixCoO2) aux mémoires Re-RAM au travers de leurs performances en termes d’endurance (nombre maximum de cycles d’écriture/effaçage), et de stabilité. En particulier, nous étudions l’influence de plusieurs paramètres (impulsions de tension, nature des électrodes, température et c…) sur ces performances. / Flash memory is now extensively used as non-volatile memory for digital data storage in most mobile electronic devices (laptop, mobile phone, tablet...). To overcome its current limits (e.g. low information density, low endurance and slow speed), many researches recently developed around the concept of resistive memories based on the switching between different resistance levels by applying appropriate bias voltages.Memories whose resistance variations depend on electrochemical reactions (ReRAM) are potentially good candidates towards next-generation non-volatile memories. The underlying redox mechanisms observed are however often of the filamentary type, involving in particular migration of cations of metal elements (coming from the electrodes), or oxygen vacancies. This filamentary character makes it challenging to attain extreme downscaling towards the nanometric scale.In this thesis, a particular class of materials - used in the field of energy storage - is studied. The aim is to investigate the origin of the resistance switching processes observed in LixCoO2 films. We first characterize the structural and electrical properties of such films, as well as the electrical behaviors of the devices elaborated therefrom. We then investigate the electrochemical mechanisms which are at the origin of resistive switching, in the micrometric electrode/film/electrode configuration. We try to determine the validity of a formerly proposed mechanism which was however not yet demonstrated. Furthermore, we study the experimental switching kinetics of devices, and propose a numerical model to explain the results observed. Finally, we examine the potential applicability of LixCoO2-based devices to Re-RAM memories through the study of their performances in terms of endurance (i.e. maximum number of write/erase cycles) and retention. Specifically, the influence of several parameters (such as voltage pulses, chemical nature of the electrodes, temperature etc.) on these performances is investigated.

The ferroelectricity in fluorite structure based hafnium oxide (HfO2) material expanded the horizon for realizing nonvolatile ferroelectric memory concepts. Due to the excellent HfO2 ferroelectric film properties, CMOS compatibility, and scalability; the material is foreseen as a replacement of the lead based ferroelectric materials with a big game changing potential for the emerging ferroelectric memories. In this thesis, the development of novel memory concepts based on the ferroelectric or antiferroelectric HfO2 material is reported. The ferroelectric field effect transistor (FeFET) memory concept offers a low power, high-speed, nonvolatile, and one cell memory solution ideal for embedded memory realization. As an emerging concept based on a novel ferroelectric material, the FeFET is challenged with key performance aspects intrinsic to the underlying physics of the device. A central part of this thesis is the development of FeFET through material and gate stack engineering, in turn leading to innovative novel device concepts. The conceptual innovation, process development, and electrical assessment are explored for an ferroelectric or antiferroelectric HfO2 based nonvolatile memories with focus on the underlying device physics. The impact of the ferroelectric material on the FeFET physics is explored via the screening of different HfO2 based ferroelectric materials, thicknesses, and the film doping concentration. The impact of material interfaces and substrate doping conditions are explored on the stack engineering level to achieve a low power and reliable FeFET. The material optimization leads to the concept of ferroelectric lamination, i.e. a dielectric interlayer between multi ferroelectric ones, to achieve a novel multilevel data storage in FeFET at reduced device variability. Toward a low power FeFET, the stack structure tuning and dual ferroelectric layer integration are explored through an MFM and MFIS integration in a single novel FeFET stack. The charge trapping effect during the FeFET switching captures the dynamics of the hysteresis polarization switching inside the stack with direct impact on the interfacial layer field. Even though manifesting as a clear drawback in FeFET operation, it can be utilized in Flash, leading to a novel hybrid low power and high-speed antiferroelectric based charge trap concept. Furthermore, the FeFET reliability is studied covering the role of operating temperature and the ferroelectric wakeup phenomenon observed in the FeFET. The temperature modulated operation, role of the high-temperature pyroelectric effect, and the temperature induced endurance and retention reliability are studied.:Table of Contents Abstract Table of Contents 1. Introduction 2. Fundamentals 2.1. Basics of Ferroelectricity 2.2. The FeFET Operation Principle and Gate Stack Theory 2.3. Structure and Outline of the PhD Thesis 3. The Emerging Memory Optimization Cycle: From Conceptual Design to Fabrication 3.1. The FeFET Conceptual Design and Layout Implementation 3.2. Gate First FeFET Fabrication: Material and Gate Stack Optimization 3.3. Novel Gate First based Memory Concepts: Device Integration and Stack Optimization 3.4. Device Characterization: Electrical Testing Schemes 4. The Emerging FeFET Memory: Material and Gate Stack Optimization 4.1. Material Aspect of FeFET Optimization: Role of the FE Material Properties 4.2. The Stack Aspect of FeFET Optimization: Role of the Interface Layer Properties 4.3. The Stack Aspect of FeFET Optimization: Role of the Substrate Implant Doping 4.4. Summary 5. A Novel Multilevel Cell FeFET Memory: Laminated HSO and HZO Ferroelectrics 5.1. The Laminate MFM and Stack Characteristics 5.2. The Laminate based FeFET Memory Switching 5.3. The Laminate FeFET Multilevel Coding Operation (1 bit, 2 bit, 3 bit/cell) 5.4. The Maximum Laminate FeFET MW Dependence on FE Stack Thickness 5.5. The Role of Wakeup and Charge Trapping 5.6. The Laminate MLC FeFET Area Dependence 5.7. The Laminate MLC Retention and Endurance 5.8. Impact of Pass Voltage Disturb on Laminate based NAND Array Operation 5.9. The Laminate FeFET based Synaptic Device 5.10. Summary 6. A Novel Ferroelectric MFMFIS FeFET: Toward Low Power and High-Speed NVM 6.1. The MFMFIS FeFET P-E and FET Characteristics 6.2. The MFMFIS based Memory Characteristics 6.3. The Impact of MFMFIS Stack Structure Tuning 6.4. The Maximum MFMFIS FeFET Memory Window 6.5. The Role of Device Scalability and Variability 6.6. The MFMFIS Area Tuning for Low Power Operation 6.7. The MFMFIS based FeFET Reliability 6.8. The Synaptic MFMFIS based FeFET 6.9. Summary 7. A Novel Hybrid Low Power and High-Speed Antiferroelectric Boosted Charge Trap Memory 7.1. The Hybrid Charge Trap Memory Switching Characteristics 7.2. The Role of Polarization Switching on Optimal Write Conditions 7.3. The Impact of FE/AFE Properties on the Charge Trap Maximum Memory Window 7.4. The Hybrid AFE Charge Trap Multi-level Coding and Array Operation 7.5. The Global Variability and Area Dependence of the Charge Trap Memory Window 7.6. The AFE Charge Trap Reliability 7.7. The Hybrid AFE Charge Trap based Synapse 7.8. Summary 8. The Emerging FeFET Reliability: Role of Operating Temperature and Wakeup Effect 8.1. The FeFET Temperature Reliability: A Temperature Modulated Operation 8.2. The FeFET Temperature Reliability: Role of the Pyroelectric Effect 8.3. The FeFET Temperature Reliability: Endurance and Retention 8.4. The Impact of Ferroelectric Wakeup on the FeFET Memory Reliability 8.5. Summary 9. Closure: What this Thesis has Solved? 9.1. How material selection/development influence the FeFET? 9.2. Why the FeFET Still Operates at High Write Conditions? 9.3. Why the FeFET Endurance is still a Challenge? 9.4. Can the FeFET become Multi-bit Storage Memory? 9.5. How the Scalability Determine FeFET Chances? 10. Summary 11. Bibliography List of symbols and abbreviations List of Publications Acknowledgment Erklärung

Der zunehmende Bedarf nach digitalen Speichermedien macht die Erforschung von neuen Materialien für zukünftige Technologien von nichtflüchtigen Speichern nötig. Hierfür eignen sich zum Beispiel Metall-Nanopartikel, die in organischen Halbleiterschichten eingebettet sind. Aufgrund der bistabilen Schaltbarkeit der Leitfähigkeit von Metall-Nanopartikeln lassen sie sich in Abhängigkeit der elektrischen Umgebungsbedingungen entweder in einen niedrig- oder einen hochleitenden Zustand schalten. Bisher wurden verschiedene Modelle entwickelt, um den Schaltmechanismus von Speichern mit einem organischen Matrixmaterial zu erklären, jedoch fehlt bislang ein konsistentes Bild zum Verständnis des Schaltvorgangs. Die vorliegende Arbeit  untersucht die Rolle des Raumladungsfeldes ausgehend von Metall-Nanopartikeln in Bauelementen. Dazu wurde eine Reihe von Experimenten zur Bestimmung der elektronischen und elektrischen Eigenschaften durchgeführt, um die tatsächliche Rolle des Raumladungsfeldes aufzuklären. Mit Hilfe von Röntgen- und UV-Photoelektronenspektroskopie wurde die Wechselwirkung zwischen den Metall-Nanopartikeln und den prototypischen organischen Halbleiterschichten detailliert untersucht. Unter Verwendung der bereits untersuchten Materialien wurden Bauelemente hergestellt und charakterisiert. Die Ergebnisse zeigen, dass der allgemein vorgeschlagene Mechanismus bezüglich der Aufladung/Entladung von Metall-Nanopartikeln als Ursache für die elektrische Bistabiliät in einem zweipoligen Bauteil ausgeschlossen werden kann. Stattdessen stützt dieses Ergebnis den alternativen Mechanismus der Filamentbildung. Zur Untersuchung der Skalierbarkeit der Speicher im Nanometerbereich wurden die Strukturen durch das Abscheiden der Materialien bei streifendem Einfall präpariert. Die entsprechenden Nanospeicher wurden elektrisch charakterisiert und zeigten Bistabilität. Folglich sind diese Nanspeicher besonders attraktiv für zukünftige Technologien in Hinblick auf hohe Speicherdichten. / The increasing need to store digital information has triggered research into the exploration of new materials for future non-volatile memory (NVM) technologies. For instance, metal nanoparticles (MNPs) embedded into organic semiconductors are suitable for novel memory applications because they were found to display bistable resistive switching. Different switching models were hitherto developed to explain the fundamental mechanisms at work in resistive NVMs. This thesis explores specifically the role of space-charge field due to the charging of MNPs as rationale for resistive switching in two-terminal devices. A series of experiments on the electronic and electrical properties of devices were conducted in order to reveal whether this mechanism is, indeed, at play in resistance switching. Photoelectron spectroscopy provided detailed information about the interaction between gold nanoparticles (AuNPs) with prototypical organic semiconductors used in optoelectronics. The study of the electronic valence structures provided evidence of a space-charge due to the charging of AuNPs. Furthermore, it is found that charge-neutrality of AuNPs can be dynamically re-established upon illumination, through electron transfer from excitons. Devices were built with the same materials investigated by photoemission spectroscopy and electrical characterization was conducted. Despite the previously demonstrated ability to optically change the charging state of the AuNPs, the devices do not display any bistability. This finding provides evidence that the commonly proposed charging/decharging mechanism of MNPs can be excluded as cause for electrical bistability in NVM devices. In order to explore the scaling of resistive NVMs into the nanometric range, glancing angle deposition technique was employed. The nano-NVMs were electrically characterized and it is proved to manifest resistive bistability. These finding make nano-NVMs highly appealing for future high-density memory technology.

With the rise of computationally expensive application domains such as machine learning, genomics, and fluids simulation, the quest for performance and energy-efficient computing has gained unprecedented momentum. The significant increase in computing and memory devices in modern systems has resulted in an unsustainable surge in energy consumption, a substantial portion of which is attributed to the memory system. The scaling of conventional memory technologies and their suitability for the next-generation system is also questionable. This has led to the emergence and rise of nonvolatile memory ( NVM ) technologies. Today, in different development stages, several NVM technologies are competing for their rapid access to the market. Racetrack memory ( RTM ) is one such nonvolatile memory technology that promises SRAM -comparable latency, reduced energy consumption, and unprecedented density compared to other technologies. However, racetrack memory ( RTM ) is sequential in nature, i.e., data in an RTM cell needs to be shifted to an access port before it can be accessed. These shift operations incur performance and energy penalties. An ideal RTM , requiring at most one shift per access, can easily outperform SRAM . However, in the worst-cast shifting scenario, RTM can be an order of magnitude slower than SRAM . This thesis presents an overview of the RTM device physics, its evolution, strengths and challenges, and its application in the memory subsystem. We develop tools that allow the programmability and modeling of RTM -based systems. For shifts minimization, we propose a set of techniques including optimal, near-optimal, and evolutionary algorithms for efficient scalar and instruction placement in RTMs . For array accesses, we explore schedule and layout transformations that eliminate the longer overhead shifts in RTMs . We present an automatic compilation framework that analyzes static control flow programs and transforms the loop traversal order and memory layout to maximize accesses to consecutive RTM locations and minimize shifts. We develop a simulation framework called RTSim that models various RTM parameters and enables accurate architectural level simulation. Finally, to demonstrate the RTM potential in non-Von-Neumann in-memory computing paradigms, we exploit its device attributes to implement logic and arithmetic operations. As a concrete use-case, we implement an entire hyperdimensional computing framework in RTM to accelerate the language recognition problem. Our evaluation shows considerable performance and energy improvements compared to conventional Von-Neumann models and state-of-the-art accelerators.