Recent theories in numerical cognition suggest that humans are equipped with a mental system that supports the representation and processing of symbolic and nonsymbolic magnitudes, called the Approximate Number System (ANS). Prior research also suggests that the acuity of the ANS can predict individuals’ mathematical ability. However, results from research within the field has proven to be inconsistent with one another which raises questions about the reliability and validity of methods used to measure the ANS. The present study attempts to replicate the results found in studies suggesting that ANS acuity correlates with mathematical ability. The study also investigates the reliability and validity of different task that have been used to measure the ANS, and also presents a new method of measuring the ANS with an adaptive method. The results show that two tasks correlate significantly with mathematical ability, and multiple regression analyses show that ANS acuity can predict mathematical ability when controlling for general intelligence. Furthermore, the results also further highlight the issue of methodological flaws in previous studies.

This thesis focuses on efficient design of a vertex shader for per-vertex operations such as Transformation and Lighting in the OpenGL ES 2.0 graphics pipeline. The vertex shader performs these complex operations using logarithmic number system, and makes partial optimization for the hardware area based on the accuracy requirement of half-precision floating-point. The vertex shader design emphasizes low cost, and is well suited to low-accuracy embedded applications. The vertex shader is an SIMD (Single-Instruction-Multiple-Data) design with customized instruction set that allows users to write efficient vertex shader programs.

Power dissipation has become one of the major limiting factors in the design of digital ASICs. Low power dissipation will increase the mobility of the ASIC by reducing the system cost, size and weight. DSP blocks are a major source of power dissipation in modern ASICs. The residue number system (RNS) has, for a long time, been proposed as an alternative to the regular two's complement number system (TCS) in DSP applications to reduce the power dissipation. The basic concept of RNS is to first encode the input data into several smaller independent residues. The computational operations are then performed in parallel and the results are eventually decoded back to the original number system. Due to the inherent parallelism of the residue arithmetics, hardware implementation results in multiple smaller design units. Therefore an RNS design requires low leakage power cells and will result in a lower switching activity. The residue number system has been analyzed by first investigating different implementations of RNS adders and multipliers (which are the basic arithmetic functions in a DSP system) and then deriving an optimal combination of these. The optimum combinations have been used to implement an FIR filter in RNS that has been compared with a TCS FIR filter. By providing different input data and coefficients to both the RNS and TCS FIR filter an evaluation of their respective performance in terms of area, power and operating frequency have been performed. The result is promising for uniform distributed random input data with approximately 15 % reduction of average power with RNS compared to TCS. For a realistic DSP application with normally distributed input data, the power reduction is negligible for practical purposes.

The system of rational numbers can be extended to the real number system by several methods. In this paper, we shall extend the rational number system by means of rational nests of intervals, and develop the elementary properties of the real numbers obtained by this extension.

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<p>The uniquely human mathematical mind sets us apart from all other animals. Although humans typically think about number symbolically, we also possess nonverbal representations of quantity that are present at birth and shared with many other animal species. These primitive numerical representations are thought to arise from an evolutionarily ancient system termed the Approximate Number System (ANS). The present dissertation aims to determine how these preverbal representations of quantity may serve as the foundation for more complex quantitative reasoning abilities. To this end, the five studies contained herein investigate the relations between representations of number, representations of other magnitude dimensions, and symbolic math proficiency in infants, children, and adults. The first empirical study, described in Chapter 2, investigated whether infants engage the ANS to represent the full range of natural numbers. The study presented in Chapter 3 compared infants' acuity for detecting changes in contour length to their acuity for detecting changes in number to assess whether representations of continuous quantities are primary to representations of number in infancy. The study presented in Chapter 4 compared individual differences in acuity for number, line length, and brightness in children and adults to determine how the relations between these magnitudes may change over development. Chapter 5 contains a longitudinal study investigating the relation between preverbal number sense in infancy and symbolic math abilities in preschool-aged children. Finally, the study presented in Chapter 6 investigated the mechanisms underlying the maturation of the number sense and determined which features of the number sense are predictive of symbolic math skill. Taken together, these findings confirm that number is a salient feature of the environment for infants and young children and suggest that approximate number representations are fundamental for the acquisition of symbolic math.</p> / Dissertation

The IEEE standard of decimal floating-point arithmetic was officially released in 2008. The new decimal floating-point (DFP) format and arithmetic can be applied to remedy the conversion error caused by representing decimal floating-point numbers in binary floating-point format and to improve the computing performance of the decimal processing in commercial and financial applications. Nowadays, many architectures and algorithms of individual arithmetic functions for decimal floating-point numbers are proposed and investigated (e.g., addition, multiplication, division, and square root). However, because of the less efficiency of representing decimal number in binary devices, the area consumption and performance of the DFP arithmetic units are not comparable with the binary counterparts. IBM proposed a binary fused multiply-add (FMA) function in the POWER series of processors in order to improve the performance of floating-point computations and to reduce the complexity of hardware design in reduced instruction set computing (RISC) systems. Such an instruction also has been approved to be suitable for efficiently implementing not only stand-alone addition and multiplication, but also division, square root, and other transcendental functions. Additionally, unconventional number systems including digit sets and encodings have displayed advantages on performance and area efficiency in many applications of computer arithmetic. In this research, by analyzing the typical binary floating-point FMA designs and the design strategy of unconventional number systems, ``a high performance decimal floating-point fused multiply-add (DFMA) with redundant internal encodings" was proposed. First, the fixed-point components inside the DFMA (i.e., addition and multiplication) were studied and investigated as the basis of the FMA architecture. The specific number systems were also applied to improve the basic decimal fixed-point arithmetic. The superiority of redundant number systems in stand-alone decimal fixed-point addition and multiplication has been proved by the synthesis results. Afterwards, a new DFMA architecture which exploits the specific redundant internal operands was proposed. Overall, the specific number system improved, not only the efficiency of the fixed-point addition and multiplication inside the FMA, but also the architecture and algorithms to build up the FMA itself. The functional division, square root, reciprocal, reciprocal square root, and many other functions, which exploit the Newton's or other similar methods, can benefit from the proposed DFMA architecture. With few necessary on-chip memory devices (e.g., Look-up tables) or even only software routines, these functions can be implemented on the basis of the hardwired FMA function. Therefore, the proposed DFMA can be implemented on chip solely as a key component to reduce the hardware cost. Additionally, our research on the decimal arithmetic with unconventional number systems expands the way of performing other high-performance decimal arithmetic (e.g., stand-alone division and square root) upon the basic binary devices (i.e., AND gate, OR gate, and binary full adder). The proposed techniques are also expected to be helpful to other non-binary based applications.

Master of Science / Department of Electrical and Computer Engineering / Balasubramaniam Natarajan / Space-time coding (STC) schemes for Multiple Input Multiple Output (MIMO) systems have been an area of active research in the past decade. In this thesis, we propose a novel design of Space-Time Block Codes (STBCs) using Redundant Residue Number System (RRNS) codes, which are ideal for high data rate communication systems. Application of RRNS as a concatenated STC scheme to a MIMO wireless communication system is the main motivation for this work. We have optimized the link between residues and complex constellations by incorporating the “Direct Mapping” scheme, where residues are mapped directly to Gray coded constellations. Knowledge of apriori probabilities of residues is utilized to implement a probability based “Distance-Aware Direct Mapping” (DA) scheme, which uses a set-partitioning approach to map the most probable residues such that they are separated by the maximum possible distance. We have proposed an “Indirect Mapping” scheme, where we convert the residues back to bits before mapping them. We have also proposed an adaptive demapping scheme which utilizes the RRNS code structure to reduce the ML decoding complexity and improve the error performance. We quantify the upper bounds on codeword and bit error probabilities of both Systematic and Non-systematic RRNS-STBC and characterize the achievable coding and diversity gains assuming maximum likelihood decoding (MLD). Simulation results demonstrate that the DA Mapping scheme provides performance gain relative to a Gray coded direct mapping scheme. We show that Systematic RRNS-STBC codes provide superior performance compared to Nonsystematic RRNS-STBC, for the same code parameters, owing to more efficient binary to residue mapping. When compared to other concatenated STBC and Orthogonal STBC (OSTBC) schemes, the proposed system gives better performance at low SNRs.