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[pt] Vários aspectos de um sistema elétrico de potência devem ser avaliados em detalhe antes de sua construção e operação. A escolha dos níveis de isolamento utilizadas é editada pelas condições em regime permanente e de sobre tensões que poderão ocorrer no sistema. Naturalmente, as linhas de transmissão veículos de transporte de energia estão intimamente ligadas a este problema. A sua perfeita operação determina níveis de atendimento apropriados aos consumidores. Portanto, é de extrema importância que se conheça o comportamento do isolamento do sistema de transmissão. O presente trabalho tem por objetivo fornecer ao engenheiro condições d analisar a performance de uma linha de transmissão quando submetida a surtos atmosféricos e a surtos de manobra através de dois programas desenvolvidos para o computador digital HP- 2100. / [en] Many aspects of an electric utility power system design must be evaluated in detail prior to construction and operation. The choice of insulation requirements on eletric utility system equipment is dictated both by the steady state conditions as well as by overvoltages which can occur on the system. Transmission lines, which are the way to carry energy, are certainly involved in this problem. Therefore it is very important to know their insulation behavior. The purpose of this work is to give the engineer conditions to analyze transmission lines behavior, by way of two digital programs, one concerning lightining strokes and the other switching surges.

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This study examined changes in task performance during performance of simulated overhead assembly task. The study objectives were to better understand the relationship between fatigue development during overhead work and task performance. This relationship is important, considering that performance changes, or decreases in task quality, have the potential for justifying and driving ergonomic changes that can help to improve worker safety. Sixteen people participated in eight experimental conditions (two levels of duty cycles, two work heights, and two hand positions). Four dependent measures based on endurance, subjective, objective, and physiological fatigue were used to quantify shoulder fatigue and were collected during the experiment. An overhead work task required participants to use a hand tool to strike targets at two reach distances above their head. Task performance was measured as a function of the closeness to the target center and the ability to apply a consistent force throughout the experiment. Data collected in this experiment is intended to provide a research basis for creating design guidelines that will help maximize efficiency and quality while reducing the likelihood of developing shoulder fatigue. / Master of Science

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Heterogeneous platforms, systems with both general-purpose processors and task-specific hardware, are largely used in industry to increase efficiency, but the heterogeneity also increases the difficulty of design and verification. We often need to wait for the completion of all the modules to know whether the functionality of the design is correct or not, which can cause costly and tedious design iteration cycles. Correctness by construction is a methodology that proposes tackling this problem by separating specification and implementation and bridging them through formal methods. Code synthesis is one of these methods which refers to the process of generating low-level codes implementing the desired system from high-level modelling languages. Formulating a generic synthesis method can, in principle, decrease error rates and shorten development cycles since target-specific usage and mechanisms can be systematically taken care of in an automatic manner, whereas the designer needs only to ensure the functional correctness of the high-level specification model. In this respect, this thesis aims to use the open-source Zero Overhead Topology Infrastructure (ZOTI) methodology to formulate a synthesis process from a denotational graph-based representation of an application, tailored towards heterogeneous hardware/software implementations. The case study presents the partially automated synthesis of an open-source streaming processing subsystem on a Xilinx Zynq-based system-on-chip architecture consisting of a software part and a custom hardware accelerator part, where both C software and VHDL hardware are generated from the input model. While the initial results demonstrate a promising path for systemizing the code generation process, certain aspects of the synthesis, such as generating glue code for complex data types (e.g., multi-arrays), are left out of the scope of this thesis and will be explored in future work. / Heterogena plattformar, system med både generella processorer och uppgiftsspecifik hårdvara, används till stor del inom industrin för att öka effektiviteten, men heterogeniteten ökar också svårigheten att designa och verifiera. Vi behöver ofta vänta på att alla moduler är färdiga för att veta om designens funktionalitet är korrekt eller inte, vilket kan orsaka kostsamma och tråkiga designiterationscykler. Korrekthet genom konstruktion är en metod som föreslår att man åtgärdar detta problem genom att separera specifikation och implementering och överbrygga dem genom formella metoder. Kodsyntes är en av dessa metoder som hänvisar till processen att generera lågnivåkoder som implementerar det önskade systemet från högnivåmodelleringsspråk. Att formulera en generisk syntesmetod kan i princip minska felfrekvensen och förkorta utvecklingscyklerna eftersom målspecifik användning och mekanismer systematiskt kan tas om hand på ett automatiskt sätt, medan designern bara behöver säkerställa den funktionella korrektheten hos högnivån. specifikationsmodell. I detta avseende syftar denna avhandling till att använda öppen källkod Zero Overhead Topology Infrastructure (ZOTI) metodiken för att formulera en syntesprocess från en denotationsgrafbaserad representation av en applikation, skräddarsydd för heterogena hårdvaru-/mjukvaruimplementationer. Fallstudien presenterar den delvis automatiserade syntesen av ett undersystem för bearbetning av strömning med öppen källkod på en Xilinx Zynq-baserad system-på-chip-arkitektur bestående av en mjukvarudel och en anpassad hårdvaruacceleratordel, där både C-programvara och VHDL-hårdvara genereras från ingångsmodellen. Även om de initiala resultaten visar en lovande väg för att systemisera kodgenereringsprocessen, lämnas vissa aspekter av syntesen, såsom generering av limkod för komplexa datatyper (t.ex. multi-arrayer), utanför ramen för denna avhandling och kommer att vara utforskas i framtida arbete.

<p dir="ltr">In the ever-changing landscape of game development, the choice of game engine plays a critical role in deciding the efficiency and performance of a game. This research paper presents a comparative analysis of the performance benchmarks of large general purpose game engines, specifically Unreal Engine 5, Unity, and Godot, versus small genre-specific engines in the context of a simple 2D projectile dodging game. The study focuses on two-dimensional games, which are particularly popular with small studios and indie developers. All three general purpose engines evaluated claim to support building both 2D and 3D applications, however since 2D game logic tends to be smaller scoped and more compact such games are impacted greater by any overhead and bloat the engine introduces, which this research paper intends to evaluate. A series of controlled experiments are conducted to assess each engine's performance in processor utilization, power consumption, memory usage and storage space requirements.</p>

One of the major advances that has been happening in the use of communication technologies, is the gradual replacement of IPv4 by the IPv6. This change provides several enhancements, although the transmission performance is relatively low, by considering the new addressing standard, which becomes 128 bits in IPv6, compared to 32 bits in IPv4, increasing the size of the resultant header and the communication overhead. This work has as main objective the development of a method for the minimization of the IPv6 header, seeking to increase the performance of data transmission in a local area network. Practical tests have shown that the proposed solution enables an improvement in network performance, increasing data throughput, in addition to decreasing latency and bandwidth utilization in the transmission of packets between two devices. / Um dos principais avanços que vem ocorrendo na utilizazação de tecnologias de comunicação, é a substituição gradativa do protocolo IPv4 pelo IPv6. Essa mudança apresenta diversas melhorias, embora o desempenho na transmissão seja relativamente menor ao considerar o novo padrão de endereçamento, que passa de 32 bits no IPv4, para 128 bits no IPv6, aumentando o tamanho do cabeçalho resultante e o overhead de comunicação. Este trabalho tem como principal objetivo o desenvolvimento de um método para a minimização do cabeçalho IPv6, buscando o aumento de desempenho na transmissão de dados em uma rede local. Testes práticos demonstraram que a solução proposta permite uma melhora de desempenho na rede, com o aumento da vazão de dados, além da diminuição da latência e da utilização de banda na transmissão de pacotes entre dois dispositivos.