Multi-core processors have become the dominant processor architecture with 2, 4, and 8 cores on a chip being widely available and an increasing number of cores predicted for the future. In addition, the decreasing costs and increasing programmability of Graphic Processing Units (GPUs) have made these an accessible source of parallel processing power in general purpose computing. Among the many research challenges that this scenario has raised are the fundamental problems related to theoretical modeling of computation in these architectures. In this thesis we study several aspects of computation in modern parallel architectures, from modeling of computation in multi-cores and heterogeneous platforms, to multi-core cache management strategies, through the proposal of an architecture that exploits bit-parallelism on thousands of bits. Observing that in practice multi-cores have a small number of cores, we propose a model for low-degree parallelism for these architectures. We argue that assuming a small number of processors (logarithmic in a problem's input size) simplifies the design of parallel algorithms. We show that in this model a large class of divide-and-conquer and dynamic programming algorithms can be parallelized with simple modifications to sequential programs, while achieving optimal parallel speedups. We further explore low-degree-parallelism in computation, providing evidence of fundamental differences in practice and theory between systems with a sublinear and linear number of processors, and suggesting a sharp theoretical gap between the classes of problems that are efficiently parallelizable in each case. Efficient strategies to manage shared caches play a crucial role in multi-core performance. We propose a model for paging in multi-core shared caches, which extends classical paging to a setting in which several threads share the cache. We show that in this setting traditional cache management policies perform poorly, and that any effective strategy must partition the cache among threads, with a partition that adapts dynamically to the demands of each thread. Inspired by the shared cache setting, we introduce the minimum cache usage problem, an extension to classical sequential paging in which algorithms must account for the amount of cache they use. This cache-aware model seeks algorithms with good performance in terms of faults and the amount of cache used, and has applications in energy efficient caching and in shared cache scenarios. The wide availability of GPUs has added to the parallel power of multi-cores, however, most applications underutilize the available resources. We propose a model for hybrid computation in heterogeneous systems with multi-cores and GPU, and describe strategies for generic parallelization and efficient scheduling of a large class of divide-and-conquer algorithms. Lastly, we introduce the Ultra-Wide Word architecture and model, an extension of the word-RAM model, that allows for constant time operations on thousands of bits in parallel. We show that a large class of existing algorithms can be implemented in the Ultra-Wide Word model, achieving speedups comparable to those of multi-threaded computations, while avoiding the more difficult aspects of parallel programming.

Thesis (M.B.A.)--University of Hong Kong, 1998. / Includes bibliographical references (leaf 86-88).

Made available in DSpace on 2016-06-02T19:06:14Z (GMT). No. of bitstreams: 1 6202.pdf: 2303544 bytes, checksum: f49c225976e9069a96200021080e9dfa (MD5) Previous issue date: 2010-08-29 / The use of computer virtualization has grown rapidly in recent years, motivating the research for software and hardware improvements to optimize performance and reduce the bottlenecks inherent of virtualization. In the middle of this decade, the processors has added support for CPU virtualization, simplifying the design of virtual machine monitors, but the employed approach had performance limitations when combined with the virtualization of memory using shadow page tables. Adding support for nested paging hardware was the answer to this problem, providing performance closer to the native, ie, without the virtual abstraction. The multicore processors were the solution to keep the microprocessors' performance growth , as the monolithic architectures were close to their limit. The use of virtualization allows exploiting parallelism offered by them through the simultaneous execution of multiple virtual machines. This study evaluates the virtualization of memory subsystem and its interaction with the multicore architectures, to determine the set of features that maximize performance. We evaluated shadow and nested paging, comparing the use of conventional and large pages to map virtualized memory. We also analyzed the influence due to the presence of a level of cache shared among cores. The results showed that in the evaluated scenario the best performance was achieved by using nested paging using large pages to map memory, while the additional level of cache didn't bring any specific benefits to virtualization. / O uso de virtualização de computadores vem crescendo rapidamente nos últimos anos, motivando a pesquisa de melhorias em software e hardware que permitam aumento de desempenho e a redução dos gargalos inerentes à virtualização. Em meados desta década, os processadores adicionaram suporte a virtualização de CPU, simplificando o projeto dos monitores de máquinas virtuais, porém o modelo adotado apresentava restrições de desempenho quando combinado com a virtualização de memória utilizando tabelas de páginas de sombra. A inclusão de suporte a paginação aninhada em hardware foi a resposta a esse problema, oferecendo desempenho mais próximo ao nativo, isto é, sem a abstração virtual. Os processadores com múltiplos núcleos, também conhecidos como multi-core, foram a solução encontrada para manter o aumento de desempenho dos microprocessadores, visto que as arquiteturas monolíticas estavam próximo ao seu limite. A utilização de virtualização permite explorar o paralelismo oferecido por eles através da execução simultânea de múltiplas máquinas virtuais. O presente trabalho avalia o subsistema de virtualização de memória e sua interação com as arquiteturas multi-core, visando determinar o conjunto de características que maximizem o desempenho. Foram avaliadas as paginações de sombra e aninhada, comparando a utilização de páginas convencionais e grandes para o mapeamento da memória virtualizada. Também foi avaliada a influência decorrente da presença de um nível de memória cache compartilhado entre os núcleos de processamento. Os resultados mostraram que no cenário avaliado o melhor desempenho foi obtido através de utilização de paginação aninhada utilizando páginas grandes para o mapeamento da memória, enquanto que o nível adicional de memória cache não trouxe benefícios específicos à virtualização.

The results of this work are two major projects - NpgObjects and PagedDataGridView. NpgObjects is a simple ORM framework to enable the mapping database tables to objects in the common language runtime. It contains a specially designed generator which generates classes in C# from information obtained from the database. These classes are mapping on the database tables one to one. NpgObjects allows all the basic database operations - SELECT, INSERT, UPDATE and DELETE. PagedDataGridView is a component for displaying tabular data. In cooperation with NpgObjects can paginate database data and manage the flow of data into application. It provides a comfortable user interface, which can easily navigate between different pages of data.

No description available.

No contexto da gerência de memória em sistemas operacionais, vários grupos de pesquisa desenvolvem trabalhos na área de algoritmos para gerência de memória virtual e alguns algoritmos para substituição de páginas têm sido propostos na literatura recente. No entanto, essas propostas não chegaram a um algoritmo que resolva satisfatoriamente o problema de desempenho na gerência de memória. Ainda não existe um consenso entre os pesquisadores de como essa questão deve ser tratada de maneira eficiente, e as propostas de algoritmos desenvolvidas possuem grande sobrecarga devido à sua complexidade. O objetivo deste trabalho é propor uma forma eficiente de gerenciar a memória com a composição de técnicas de busca, posicionamento e substituição de páginas. A hipótese aqui adotada é que para tratar o problema da gerência da memória é melhor consumir recursos computacionais determinando quais páginas deveriam estar na memória em um determinado instante de tempo do que gastar recursos determinando qual página será retirada da memória. A tese apresenta uma reanálise dos principais trabalhos que têm como objetivo o desempenho da gerência de memória, tornando possível retirar conclusões e ideias sobre quais fatores influenciam de maneira positiva com relação ao desempenho do sistema. A partir deste estudo, é determinado o conceito de qualidade do conteúdo da memória e criada uma métrica para medi-la. Aplicando tal conceito, formula-se um método sistêmico de construção de algoritmos de gerência de memória. Realiza-se uma aplicação desse método, criando-se então, os algoritmos RR+ng e RRlock+ng. A métrica é aplicada em simulações na fase final do método, mostrando-se adequada para realizar as análises. Os resultados obtidos mostram que a hipótese tratar o problema da gerência da memória, consumindo recursos computacionais determinando quais páginas devem estar na memória ao invés de quais devem deixá-la mostrou-se válida e parece promissora. / When it comes to memory management in operating systems, many research groups have been developing works in the memory management algorithms area and some page replacement algorithms have been proposed in the recent literature. Such proposals were not successful in developing algorithms that worked well as far as the performance in memory management is concerned. There is no consensus among the researches about how this problem can be treated efficiently, and the algorithms proposed have high overhead because of their complexity. The objective of this work is to propose an efficient memory management with the composition of page fetch, placement and replacement techniques. This thesis hypothesis is that to treat the memory management problem it is better to consume computational resources determining which pages must be in the memory in a given time than to waste resources defining which pages would be evicted from the memory. This work presents a reanalysis of the main works whose objective is memory management performance, making it possible to draw different conclusions and ideas about what factors may have a positive influence with respect to system performance. This study develops both the concept of quality of memory contents and a metric to measure it. Besides, a systemic method to create memory management algorithms is devised, applying the concept just created. Then, the method is followed, creating the RR+ng and RRlock+ng algorithms. In the final phase of the method, the metric is applied in simulations, proving to be adequate to perform the analysis. The results show that the idea of treating the memory management problem, consuming computational resources to determine which pages must be in the memory instead of which ones must leave it, hold true and seems to be promising.

No contexto da gerência de memória em sistemas operacionais, vários grupos de pesquisa desenvolvem trabalhos na área de algoritmos para gerência de memória virtual e alguns algoritmos para substituição de páginas têm sido propostos na literatura recente. No entanto, essas propostas não chegaram a um algoritmo que resolva satisfatoriamente o problema de desempenho na gerência de memória. Ainda não existe um consenso entre os pesquisadores de como essa questão deve ser tratada de maneira eficiente, e as propostas de algoritmos desenvolvidas possuem grande sobrecarga devido à sua complexidade. O objetivo deste trabalho é propor uma forma eficiente de gerenciar a memória com a composição de técnicas de busca, posicionamento e substituição de páginas. A hipótese aqui adotada é que para tratar o problema da gerência da memória é melhor consumir recursos computacionais determinando quais páginas deveriam estar na memória em um determinado instante de tempo do que gastar recursos determinando qual página será retirada da memória. A tese apresenta uma reanálise dos principais trabalhos que têm como objetivo o desempenho da gerência de memória, tornando possível retirar conclusões e ideias sobre quais fatores influenciam de maneira positiva com relação ao desempenho do sistema. A partir deste estudo, é determinado o conceito de qualidade do conteúdo da memória e criada uma métrica para medi-la. Aplicando tal conceito, formula-se um método sistêmico de construção de algoritmos de gerência de memória. Realiza-se uma aplicação desse método, criando-se então, os algoritmos RR+ng e RRlock+ng. A métrica é aplicada em simulações na fase final do método, mostrando-se adequada para realizar as análises. Os resultados obtidos mostram que a hipótese tratar o problema da gerência da memória, consumindo recursos computacionais determinando quais páginas devem estar na memória ao invés de quais devem deixá-la mostrou-se válida e parece promissora. / When it comes to memory management in operating systems, many research groups have been developing works in the memory management algorithms area and some page replacement algorithms have been proposed in the recent literature. Such proposals were not successful in developing algorithms that worked well as far as the performance in memory management is concerned. There is no consensus among the researches about how this problem can be treated efficiently, and the algorithms proposed have high overhead because of their complexity. The objective of this work is to propose an efficient memory management with the composition of page fetch, placement and replacement techniques. This thesis hypothesis is that to treat the memory management problem it is better to consume computational resources determining which pages must be in the memory in a given time than to waste resources defining which pages would be evicted from the memory. This work presents a reanalysis of the main works whose objective is memory management performance, making it possible to draw different conclusions and ideas about what factors may have a positive influence with respect to system performance. This study develops both the concept of quality of memory contents and a metric to measure it. Besides, a systemic method to create memory management algorithms is devised, applying the concept just created. Then, the method is followed, creating the RR+ng and RRlock+ng algorithms. In the final phase of the method, the metric is applied in simulations, proving to be adequate to perform the analysis. The results show that the idea of treating the memory management problem, consuming computational resources to determine which pages must be in the memory instead of which ones must leave it, hold true and seems to be promising.

This is a report on research regarding the screen layout of Web-based training (WBT) programs, conducted with an eye toward providing evidence-based guidance for the design and development of WBT interfaces. Specifically, the study investigated the relative instructional benefits of two general types of WBT screen design, full-page and partial-page, in terms of both learner performance and learner satisfaction. The main hypotheses of the study were that the full-page design option would yield significantly better outcomes in both categories of interest.The study employed a mixed-method design, generating both quantitative and qualitative data. The main phase of the study was experimental, following a factorial design to explore the relationships between a single treatment variable (WBT screen design) in two treatment conditions (partial-page WBT design and full-page WBT design) and two dependent variables (learner performance and learner satisfaction). Both a full-page and a partial-page version of the same Web-based tutorial were created, and 129 self-selected undergraduate students who reported having little or no experience with the tutorial subject matter were randomly assigned into the two treatment groups. Performance data were collected as scores on the tutorial's 18-item, multiple choice final exam, and satisfaction data were collected via a 10-item satisfaction survey. In addition, 59 of the study participants were randomly selected to participate in post-study session interviews.The results of the study yielded no significant difference between the two treatment groups for either learner performance or learner satisfaction; thus, making it impossible to reject the null hypothesis for either of the two primary research questions. The conclusion of this study was that the presence or absence of scrolling alone is not a significant factor either in how well a person performs in a WBT program or how satisfied they are with the learning experience . However, while analysis of the post-study session interview data supported this conclusion, the fact that a large majority of the interviewees stated a preference for the full-page, non-scrolling WBT interface design suggests that some elements inherent in the full-page design might warrant further consideration and/or study.

Thesis (M.B.A.)--University of Hong Kong, 1992.

This master's thesis deals with design and implementation of educational application forpaging. Goal of the application is to help students understand and practice some conceptsfrom paging. It will allow students to write parts of these concepts and see how their codework on visualization of simulation of memory system. Application will be implemented asa web application in HTML, CSS and JavaScript. Server, which will be taking care ofcompiling of user code will be a desktop application. This thesis mainly describes pagingand technologies which will be used for this thesis and application design. It also describesimplementations and testing of this work.