<p>Timing-related defects are becoming increasingly important in nanometer-technology integrated circuits (ICs). Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. All these effects are noticeable in today's technologies and they are likely to become more prominent in the next-generation process technologies~\cite{itrs2007}.</p><p>The detection of small-delay defects (SDDs) is difficult because of the small size of the introduced delay. Although the delay introduced by each SDD is small, the overall impact can be significant if the target path is critical, has low slack, or includes many SDDs. The overall delay of the path may become larger than the clock period, causing circuit failure or temporarily incorrect results. As a result, the detection of SDDs typically requires fault excitation through least-slack paths. However, widely-used automatic test-pattern generation (ATPG) techniques are not effective at exciting small delay defects. On the other hand, the usage of commercially available timing-aware tools is expensive in terms of pattern count inflation and very high test-generation times. Furthermore, these tools do not target real physical defects.</p><p>SDDs are induced not only by physical defects, but also by run-time variations such as crosstalk and power-supply noise. These variations are ignored by today's commercial ATPG tools. As a result, new methods are required for comprehensive coverage of SDDs.</p><p>Test data volume and test application time are also major concerns for large industrial circuits. In recent years, many compression techniques have been proposed and evaluated using industrial designs. However, these methods do not target sequence- or timing-dependent failures while compressing the test patterns. Since timing-related failures in high-performance integrated circuits are now increasingly dominated by SDDs, it is necessary to develop timing-aware compression techniques.</p><p>This thesis addresses the problem of selecting the most effective test patterns for detecting SDDs. A new gate and interconnect delay-defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from a large pattern set generated using timing-unaware ATPG. It offers significantly lower computational complexity and it excites a larger number of long paths compared to previously proposed timing-aware ATPG methods. It is shown that, for the same pattern count, the selected patterns are more effective than timing-aware ATPG for detecting small delay defects caused by resistive shorts, resistive opens, process variations, and crosstalk. The proposed technique also serves as the basis for an efficient SDD-aware test compression scheme. The effectiveness of the proposed technique is highlighted for industrial circuits.</p><p>In summary, this research is targeted at the testing of SDDs caused by various underlying reasons. The proposed techniques are expected to generate high-quality and compact test patterns for various types of defects in nanometer ICs. The results of this research are expected to provide low-cost and effective test methods for nanometer devices, and they will lead to higher shipped-product quality.</p> / Dissertation

The elimination of distribution inefficiencies, occurring due to the timing of customers' orders is an important reason for companies to introduce vendor managed inventory programs. By managing their customers' inventories, suppliers may be able to reduce demand variability and therefore distribution costs. We develop technology to measure the effectiveness of distribution strategies. We develop a methodology that allows the computation of tight lower bounds on the total mileage required to satisfy customer demand over a period of time. As a result, companies will be able to gain insight into the effectiveness of their distribution strategy. This technology can also be used to suggest desirable delivery patterns and to analyze tactical and strategic decisions. Secondly, we study the inventory routing problem with continuous moves (IRP-CM). The typical inventory routing problem deals with the repeated distribution of a single product, from a single facility, with an unlimited supply, to a set of customers that can all be reached with out-and-back trips. Unfortunately, this is not always the reality. We introduce the IRP-CM to study two important real-life complexities: limited product availabilities at facilities and customers that cannot be served using out-and-back tours. We need to design delivery tours spanning several days, covering huge geographic areas, and involving product pickups at different facilities. We develop a heuristic and an optimization algorithm to construct distribution plans. The heuristic is an innovative randomized greedy algorithm, which includes linear programming based postprocessing technology. To solve the IRP-CM to optimality, we give a time-discretized integer programming model and develop a branch-and-cut algorithm. As instances of time-discretized models tend to be large we discuss several possibilities for reducing the problem size. We introduce a set of valid inequalities, called delivery cover inequalities, in order to tighten the bounds given by the LP relaxation of the time-discretized model. We also introduce branching schemes exploiting the underlying structure of the IRP-CM. An extensive computational study demonstrates the effectiveness of the optimization algorithm. Finally, we present an integrated approach using heuristics and optimization algorithms providing effective and efficient technology for solving inventory problems with continuous moves.