Point-of-load (POL) converters have been used extensively in IT products. Today, almost every microprocessor is powered by a multi-phase POL converter with high output current, which is also known as voltage regulator (VR). In the state-of-the-art VRs, the circuits are mostly constructed with discrete components and situated on the motherboard, where it can occupy more than 1/3 of the footprint of the motherboard. A compact POL is desirable to save precious space on motherboards to be used for some other critical functionalities. Recently, industry has released many modularized POL converters, in which the bulky inductor is integrated with the active components to increase the power density. This concept has been demonstrated at current levels less than 5A and power density around 600-1000W/in³. This might address the needs of small hand-held equipment such as smart phones, but it is far from meeting the needs for the applications such as laptops, desktops and servers, where tens and hundreds of amperes are needed. A 3D integrated POL module with an output current of tens of ampere has been successfully demonstrated at the Center for Power Electronic Systems (CPES), Virginia Tech. In this structure, the inductor is elaborated with low temperature co-fire ceramic (LTCC) ferrite, as a substrate where the active components are placed. The lateral flux inductor is proposed to achieve both a low profile and high power density. Generally, the size of the inductor can be continuously shrunk by raising the switching frequency. The emerging gallium-nitride (GaN) power devices enable the creation and use of a multi-MHz, high efficiency POL converter. This dissertation firstly explores the LTCC inductor substrate design in the multi-MHz range for a high-current POL module with GaN devices. The impacts of different frequencies and different LTCC ferrite materials on the inductor are also discussed. Thanks to the DC flux cancellation effect, the inverse coupled inductor further improves the power density of a 20A, 5MHz two-phase POL module to more than 1kW/in³. An FEA simulation model is developed to study the core loss of the lateral flux coupled inductor, which shows the inverse coupling is also beneficial for core loss reduction. The ceramic-based 3D integrated POL module, however, is not widely adopted in industrial products because of the relatively high cost of the LTCC ferrite material and complicated manufacturing process. To solve that problem, a printed circuit board (PCB) inductor substrate with embedded alloy flake composite core is proposed. The layerwise magnetic core is laminated into a multi-layer PCB, and the winding of the inductor then is formed by the copper layers and conventional PCB vias. As a demonstration of system integration, a 20A, 1.5MHz integrated POL module is designed and fabricated based on a 4-layer PCB with embedded flake core, which realizes more than 85% efficiency and 600W/in³ power density. The application of standardized PCB processes reduces the cost for manufacturing the integrated modules due to the easy automation and the low temperature manufacturing process. Combining the PCB-embedded coupled inductor substrate and advanced control strategy, the two-phase 40A POL modules are elaborated as a complete integrated laptop VR solution. The coupled inductor structure is slightly modified to improve its transient performance. The nonlinearity of the inductance is controlled by adding either air slots or low permeability magnetic slots into the leakage flux path of the coupled inductor. Then the leakage flux, which determines the transient response of the coupled inductor, can be well controlled. If we directly replace the discrete VR solution with the proposed integrated modules, more than 50% of the footprint on the motherboard can be saved. Although the benefits of the lateral flux inductor have been validated in terms of its high power density and low profile, the planar core is excited under very non-uniform flux. Some parts of the core are even pushed into the saturation region, which totally goes against the conventional sense of magnetic design. The final part of this dissertation focuses on evaluating the performance of the planar core with variable flux. The counterbalance between DC flux and AC flux is revealed, with which the AC flux and the core loss density are automatically limited in the saturated core. The saturation is essentially no longer detrimental in this special structure. Compared with the conventional uniform flux design, the variable flux structure extends the operating point into the saturation region, which gives better utilization of the core. In addition, the planar core with variable flux also provides better thermal management and more core loss reduction under light load. As conclusions, this research first challenges the conventional magnetic design rules, which always assumes uniform flux. The unique characteristics and benefits of the variable flux core are proved. As an example of taking advantages of the lateral flux inductor, the PCB integrated POL modules are proposed and demonstrated as a high-density VR solution. The integrated modules are cost-effective and ready to be commercialized, which could enable the next technological innovation for the whole computing and telecom industry. / Ph. D.

Today, every microprocessor is powered with a Voltage Regulator (VR), which is also known as a high current Point-of-Load converter (POL). These circuits are mostly constructed using discrete components, and populated on the motherboard. With this solution, the passive components such as inductors and capacitors are bulky. They occupy a considerable footprint on the motherboard. The problem is exacerbated with the current trend of reducing the size of all forms of portable computing equipment from laptop to netbook, increasing functionalities of PDA and smart phones. In order to solve this problem, a high power density POL needs to be developed. An integration solution was recently proposed to incorporate passive components, especially magnetic components, with active components in order to realize the needed power density for the POL. Today's discrete VR only has around 100W/in3 power density. The 3D integration concept is widely used for low current integrated POL. With this solution, a very low profile planar inductor is built as a substrate for the active components of the POL. By doing so, the POL footprint can be dramatically saved, and the available space is also fully utilized. This 3D integrated POL can achieve 300-1000W/in3 power density, however, with considerably less current. This might address the needs of small hand-held equipment such as PDA and Smart phone type of applications. It does not, however, meet the needs for such applications as netbook, laptop, desk-top and server applications where tens and hundreds of amperes are needed. So, although the high density integrated POL has been demonstrated at low current level, magnetic integration is still one of the toughest barriers for integration, especially for high current POL. In order to alleviate the intense thirst from the computing and telecom industry for high power density POL, the 3D integration concept needs be extended from low current applications to high current applications. The key technology for 3D integration is the low profile planar inductor design. Before this research, there was no general methodology to analyze and design a low profile planar inductor due to its non-uniform flux distribution, which is totally different as a conventional bulky inductor. A Low Temperature Co-fired Ceramic (LTCC) inductor is one of the most promising candidates for 3D integration for high current applications. For the LTCC inductor, besides the non-uniform flux, it also has non-linear permeability, which makes this problem even more complicated. This research focuses on penetrating modeling and design barriers for planar magnetic to develop high current 3D integrated POL with a power density dramatically higher than today's industry products in the same current level. In the beginning, a general analysis method is proposed to classify different low profile inductor structures into two types according to their flux path pattern. One is a vertical flux type; another one is a lateral flux type. The vertical flux type means that the magnetic flux path plane is perpendicular with the substrate. The lateral flux type means that the magnetic flux path plane is parallel with the substrate. This analysis method allows us to compare different inductor structures in a more general way to reveal the essential difference between them. After a very thorough study, it shows that a lateral flux structure is superior to a vertical flux structure for low profile high current inductor design from an inductance density point of view, which contradicts conventional thinking. This conclusion is not only valid for the LTCC planar inductor, which has very non-linear permeability, but is also valid for the planar inductor with other core material, which has constant permeability. Next, some inductance and loss models for a planar lateral flux inductor with a non-uniform flux are also developed. With the help of these models, different LTCC lateral flux inductor structures (single-turn structure and multi-turn structures) are compared systematically. In this comparison, the inductance density, winding loss and core loss are all considered. The proposed modeling methodology is a valuable extension of previous uniform flux inductor modeling, and can be used to solve other modeling problems, such as non-uniform flux transformer modeling. After that, a design method is proposed for the LTCC lateral flux inductor with non-uniform flux distribution. In this design method, inductor volume, core thickness, winding loss, core loss are all considered, which has not been achieved in previous conventional inductor design methods. With the help of this design method, the LTCC lateral flux inductor can be optimized to achieve small volume, small loss and low profile at the same time. Several LTCC inductor substrates are also designed and fabricated for the 3D integrated POL. Comparing the vertical flux inductor substrate with the lateral flux inductor substrate, we can see a savings of 30% on the footprint, and a much simpler fabrication process. A 1.5MHz, 5V to 1.2V, 15A 3D integrated POL converter with LTCC lateral flux inductor substrate is demonstrated with 300W/in3 power density, which has a factor of 3 improvements when compared to today's industry products. Furthermore, the LTCC lateral flux coupled inductor is proposed to further increase power density of the 3D integrated POL converter. Due to the DC flux cancelling effect, the size of LTCC planar coupled inductor can be dramatically reduced to only 50% of the LTCC planar non-coupled inductor. Compared to previous vertical flux coupled inductor prototypes, a lateral flux coupled inductor prototype is demonstrated to have a 50% core thickness reduction. A 1.5MHz, 5V to 1.2V, 40A 3D integrated POL converter with LTCC lateral flux coupled inductor substrate is demonstrated with 700W/in3 power density, which has a factor of 7 improvements when compared to today's industry POL products in the same current level. In conclusion, this research not only overcame some major academia problems about analysis and design for planar magnetic components, but also made significant contributions to the industry by successfully scaling the integrated POL from today's 1W-5W case to a 40W case. This level of integration would significantly save the cost, and valuable motherboard real estate for other critical functions, which may enable the next technological innovation for the whole computing and telecom industry. / Ph. D.

The miniaturization of electronics packaging is an ongoing trend. The manufacturers are increasing the packaging density to accommodate for more complex designs and increase in operating frequencies. The surface mount devices (SMDs) and today's manufacturing processes are starting to become a limiting factor to this miniaturization. The solution to these problems are embedded passives and new fully-additive manufacturing processes. In this work, a planar inductor is fabricated using a fully-additive process called Sequential Build-Up - Covalent Bonded Metallization (SBU-CBM). A new grafting material for the CBM process is tested, but found to be worse than the previously used one when tested on FR4 substrates. The best design of a planar inductor for high inductance and high Q factor is found to be the circular spiral inductor. A planar circular spiral inductor with a feature size of 75 µm is successfully fabricated using the SBU-CBM process.

Cette thèse s’inscrit dans le contexte d’alimentation des systèmes électroniques portables à faible puissance (1W environ) et fonctionnant sous faible tension. Avec la demande croissante pour la conversion d’énergie dans ces systèmes, l’intégration et la miniaturisation du convertisseur DC-DC devient une zone d’intérêt fort. Des recherches récentes ont montré des convertisseurs avec des fréquences de commutation pouvant atteindre 100 MHz. Pour de faibles niveaux de tension (1 V) et des puissances aux environs du Watt, les valeurs d’inductance de lissage de ces convertisseurs envisagées sont de l’ordre d’une centaine de nanoHenry. Ceci relance l’intérêt d’étudier l’intégration des composants passifs de dimensions millimétriques au sein d’un même boîtier avec les parties actives. Dans ce contexte, les travaux présentés dans ce manuscrit sont abordés par la conception d’inductances planaires en forme de spirale avec un noyau magnétique. Les simulations ont permis d’analyser les liens entre les paramètres géométriques et les paramètres électriques de l’inductance pour établir une structure d’inductance optimale en fonction de la limite de la technologie de réalisation. Une inductance planaire prise en sandwich entre deux couches de matériau magnétique est proposée. Les simulations ont montré l’intérêt de réaliser un tel composant. Sa structure présente plusieurs avantages, elle permet d’augmenter considérablement la valeur d’inductance tout en gardant le même encombrement par rapport à une inductance sans noyau magnétique. Elle permet également de réduire les perturbations électromagnétiques avec les composants environnants. Un procédé technologique de réalisation des inductances, basé sur la croissance électrolytique de cuivre à température ambiante, a été développé et optimisé pour valider les modélisations précédentes. Ce procédé est reproductible et permet une fabrication collective de composants. Un banc de caractérisation impédance métrique a également été conçu afin de déterminer les limites du fonctionnement fréquentiel des composants réalisés et de valider les performances de ces derniers. Ce travail propose une solution pour la réalisation de la puce active sur l’inductance dans le cadre d’un SOC (System-On-Chip). Il souligne par ailleurs l’importance de l’intégration pour l’électronique de faible puissance / The work in this thesis contributes to the domain of low power (1W approximately) portable electronic systems. These systems require integrated and miniaturized of DC-DC converters. Recent studies have demonstrated converters with high switching frequency as high as 100 MHz, requiring smaller passive components. For low voltage values (1V approximately) and 1 watt output power, the inductance value of these converter filters is about a hundred nanoHenry. Such inductors can be integrated on a millimetric scale in the same package as the active die. In this context, the work presented in this thesis starts with the design of planar spiral inductors with a magnetic core. Simulations allowed to analyze the relation between geometrical and electrical parameters of the inductor in order to design an optimal inductor. A planar inductor sandwiched between two layers of magnetic material is proposed. Simulations showed the advantages of fabricating of such component. Its structure allows to increase the inductance value without modifying the inductor’s surface compared to a coreless inductor. It also allows to reduce the electromagnetic interferences with the rest of the circuit. A technological process for the fabrication of the inductors has been developed and optimized in order to valid the previous design. This process is based on copper electroplating technique which is compatible with a repeatable and a mass fabrication of inductors. A characterization bench was also developed in order to determine the operating frequency limits of the fabricated components as well as to validate their performance. This work offers a solution for the realization of the active chip on the inductor (SOC, System- On-Chip). It also emphasizes the importance of the integration for low power electronics