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In this thesis, we will investigate the degradation of the Low-Temperature-Polycrystalline-Silicon TFTs(LTPS TFTS) under the electrical stress. The devices are offer by Chi Mei Optoelectronics. The two mechanisms of the electrical stress are ac and dc stress. On the dc stress, we can separate the two degradation mechanisms from fixed drain voltage and various the gate voltage. The first mechanism is hot carrier effect, and second is self-heating effect. We were study the degradation mechanisms cause by above-mentioned phenomenon. On the other hand, we were confirmed the position and type of the defects by measured capacitance. In the ac stress, device degradation depends on the emission rate and energy of the hot carrier. We will study the degradation mechanism which fixed the drain voltage and various the Vg_low and falling time under different temperature. Another way of the ac stress condition will be used here. The drain and source are directly connected to ground. The gate is directly connected to the pulse. At this stress condition, carrier will push to the junction near the drain and source when gate pulse is switch from high to low. This degradation mechanism is the function of the temperature. We are going to employ a C-V measurement to examination of the defect cause by stress.

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Résumé en français / Résumé en anglais

Long the dominant method of wafer planarization in the integrated circuit (IC) industry, chemical-mechanical polishing is starting to play an important role in microelectromechnical systems (MEMS). We present an experiment to characterize a polysilicon CMP process with the specific goal of examining MEMS sized test structures. We utilize previously discussed models and examine whether the same assumptions from IC CMP can be made for MEMS CMP. We find that CMP at the MEMS scale is not just pattern density dependent, but also partly dependent on feature size. Also, we find that new layout designs relevant to MEMS can negatively impact how well existing CMP models simulate polishing, motivating the need for further model development. / Singapore-MIT Alliance (SMA)

In this thesis, we study the electrical characteristics of a series of polysilicon thin-film transistors (poly-Si TFTs) with different numbers of multiple channels of various widths, with lightly-doped drain (LDD) structures. Among all investigated TFTs, the nano-scale TFT with ten 67 nm-wide split channels (M10) has superior and more uniform electrical characteristics than other TFTs, such as a higher ON/OFF current ratio (>109), a steeper subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL) and a suppressed kink-effect. These results originate from the fact that the active channels of M10 TFT has best gate control due to its nano-wire channels were surrounded by tri-gate electrodes. Additionally, experimental results reveal that the electrical performance of proposed TFTs enhances with the number of channels from one to ten strips of multiple channels sequentially, yielding a profile from a single gate to tri-gate structure. In addition, we have also studied the multi-gate combining the pattern-dependent nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels. Experimental results reveal that applying ten nanowire channels improves the performance of Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current and a lower threshold voltage (Vth) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multi-gate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low Vth, a steep subthreshold swing (SS) and kink-free output characteristics. The multi-gate with ten nanowire channels NI-MILC TFTs has few poly-Si grain boundary defects, a low lateral electrical field and a gate channel shortening effect, all of which are associated with such high-performance characteristics. The PDMILC TFTs process is compatible with CMOS technology, and involves no extra mask. Such high performance PDMILC TFTs are thus promising for use in future high-performance poly-Si TFT applications, especially in AMLCD and 3D MOSFET stacked circuits. Otherwise, we have investigated the mechanism of the leakage currents in polysilicon TFT with different temperature and applied biases. Moreover, we have simulated the electric fields in different structure polysilicon TFT to explain the mechanism of the leakage currents. By comparing the leakage currents in different channel structures, the leakage current in nanowire channel structure is higher than that in non-nanowire channel structure. Moreover, the leakage current in multiple gate structure is lower than that in single gate structure. Therefore, these two experimental results are caused by high electric field in the drain-to-gate overlap and drain-to-body depletion region respectively.

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On-chip characterization devices have been used to extract the Young’s modulus, average stress and stress gradient of polysilicon doped with phosphorus using thermal diffusion. Devices for extracting the Young’s modulus, average stress and stress gradients have been designed to work within the range of expected material property values. A customized fabrication process was developed and the devices were fabricated. Static and resonant tests were performed using clamped-clamped and cantilever beams in order to extract material properties. The experimental setup and detailed experimental results and analysis are outlined within. Several doping concentrations have been studied and it has been concluded that the Young’s modulus of polysilicon doped for 2 hours increases by approximately 50GPa and the average stress of polysilicon doped for 2.5 hours becomes more tensile by approximately 63 MPa. It has also been found that short doping times can introduce a large enough stress gradient to create a concave up curvature in free-standing structures. This work was performed in order to determine the usability of doping as a means to increase the sensitivity of temperature and pressure sensors for harsh environments. It has been concluded that doping is a promising technique and is worth studying further for this purpose.

In this thesis, we propose a simple trench oxide layer polysilicon thin-film Transistor (TO TFT) process and the self-heating effects can be significantly reduced because of its structural advantages. According to the ISE-TCAD simulation results, our proposed TO TFT structure has novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (~ 84%) and the retention time (~ 57%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

The biological treatment is one of the commonly methods of wastewater treatment plant in wastewater treatment processes. The biological treatment can meet water quality standards required by the plant in response to different sewage conditions and qualities. It can purify high pollution loading sewage through the use of microbial metabolic transformation. Through effectively protecting and using water resources, the ecological balance of ocean and river can be maintained and environmental quality can be improved in consequence. This study analyzes the operations of a wastewater treatment plant, which is part of an urban sewage system. The major sources of inflow to the plant are domestic sewage, followed by rainfall runoff and industrial wastewater. The biological treatment system adopted in the plant is "Biological Nutrient Removal (BNR)". The reason for using BNR is to prevent eutrophication of downstream water bodies due to untreated nitrogen, phosphorus and other nutrient substances in discharged sewages. The design of BNR, which is called "A2O activated sludge method", would increase the anaerobic-anaerobic mixing process for simultaneous removal of the sewage of organic carbon, nitrogen, phosphorus and BOD. The study collected the data to analyze the impacts of extreme weather event, i.e. Typhoon Morakot, and the effects of newly developed industrial, i.e. polysilicon industry. Water quality data of inflow and outflow sewages starting from January 2009 to December 2011 were compiled to perform statistical analyses. By plotting various time series figures, the study can effectively explore the variations of pollutant removal under the two designated situations in the biological treatment system. The results show the abnormal increase in conductivity of effluent which has decreased pollutant removal since August 2010. Besides, the confluence of rainwater and sewage has severely affected the efficiency and quality of the biological treatment process during a typhoon or heavy rain event. This study has identified the potential impacts on a BNR plant which can provide the administration to enhance the effectiveness of the biological treatment plant and the function of sewage purification stability control.