In this research a state-of-the-art micro-thermal conductivity detector is developed based on MEMS technology. Its efficient design include a miniaturized 100×2 µm bridge from doped polysilicon, suspended 10 µm away from the single crystalline silicon substrate through a thermally grown silicon dioxide sacrificial layer. The microbridge is covered by 200 nm silicon nitride layer to provide more life time. Analytical models were developed that describe the relationship between the sensor response and ambient gas material properties. To obtain local temperature distribution and accurate predictions of the sensor response, a computational three dimensional simulation based on real geometry and minimal simplifications was prepared. It was able to handle steady-state and transient state, include multiple physics such as flow, heat transfer, electrical current and thermal stresses. Two new methods of measurement for micro TCD were developed; a time resolved method based on transient response of the detector to a step current pulse was introduced that correlates time constant of the response to the concentration of gas mixture. The other method is based on AC excitation of the micro detector; the amplitude and phase of the third harmonic of the resulting output signal is related to gas composition. Finally, the developed micro-sensor was packaged and tested in a GC system and was compared against conventional and complex FID for the detection of a mixture of VOCs. Moreover compact electronics and telemetry modules were developed that allow for highly portable applications including microGC utilization in the field.

Recently, active matrix flat-panel displays are widely used in consumer electronic products. With increasing popularity of flat-panel displays, market competition becomes more intense and demands for high performance flat-panel displays are increasing. Low-temperature polysilicon (LTPS) with higher mobility, as well as drive current can integrate electric circuit, such as controllers and memory on glass substrate of display to achieve the purpose of system on panel (SOP). Thus, flat-panel displays can be more compact, while reducing reliability issues and lowering production costs. In this dissertation, we studied the nonvolatile memory for system on panel applications and reducing cost of memory by increasing the memory density or reducing the processing steps. Therefore, we proposed several modes of operation in nonvolatile memory. First, we use channel hot-electron (CHE) to inject electrons into the nitride layer that¡¦s above source or drain sides of SONOS thin film transistor (TFT). Thus, we can increase the memory density by storing two-bit state in a memory cell. In this study, the two-bit memory effect is clearly observed for devices with a shorter gate length after CHE programming; however, the two-bit memory effect is absent in devices with a longer gate length. The gate-length-dependent two-bit memory effect is related to the location of injected electrons in the nitride layer. When electrons are injected into the nitride layer above the channel, they can create an additional energy barrier in the channel thus increasing the threshold voltage of the device to perform the programming operations. However, if electrons are injected into the depletion region at the P-N junction between the drain and the channel, the energy barrier induced by electrons is not significant when exchanging the source and drain electrodes to measure the memory status, and the program effect is not as significant. When the channel length is shorten, the built-in potential between the source and the channel can be decreased, the energy barrier caused by programmed electrons can affect electrons in the channel and increase the threshold voltage. Therefore, the two-bit memory effect can be seen in devices with the shorter gate length after CHE programming. Secondly, we stored charges in the body of the thin film transistor to make the conventional thin-film transistors become a non-volatile memory. This method does not need a floating gate or a tunneling oxide in the memory cell; therefore the memory cost can be reduced. In this study, we used trap-assisted band-to-band thermionic field emission enhanced by self-heating in TFT to produce electron-hole pairs. The hole will be separated by a vertical field under the gate and be injected into the body of TFT to complete the programming operation. The erasing operation is performed by applying a lateral electric field between the source/drain to remove holes in the body of TFT. Thirdly, we proposed an edge-FN tunneling method to allow SONOS TFT possess not only a pixel switch but also a two-bit nonvolatile memory function in a display panel, thus causing the memory density to increase. In this study, we used a channel FN tunneling to program the SONOS TFT. Because the electric field in the gate-to-drain overlap region is larger than that in the channel region, it will cause a smoother electron injection into the nitride layer inside of the gate-to-drain overlap region, which also increases the gate-induced drain leakage (GIDL) current. The edge-FN tunneling method is used to erase electrons in the gate-to-drain overlap region, by doing so, the GIDL current has decreased. The memory status at the source/drain side is determined by the corresponding GIDL current of the SONOS TFT. Fourthly, we stored electrons in the nitride layer at source, channel, and drain regions of SONOS TFT to make sure that TFT possess a three-bit memory effect in a unitary cell, which also allows the memory density to increase significantly. In this study, programming and erasing operations in the source/drain region are performed by channel hot-electron injection and edge-FN tunneling method, while that in the channel region are accomplished by channel FN tunneling. The memory status in the source/drain is determined by the corresponding GIDL current, while that in the channel region by threshold voltage of the device The memory density for the device operated by proposed method can be further increased. In addition, if we store a number of N different types of electrons in those three regions mentioned above, there are N3 status can be stored in a memory cell. The memory density can beyond conventional multi-level-cell (MLC) flash memory. Two-bit memory effect per cell in a MLC flash memory can be achieved by storing four quantitative electrons in the floating gate of the memory device. If we store four quantitative electrons in the nitride layer at source, channel, and drain regions of SONOS TFT, we can obtain 64 memory states or 6-bit memory effect in a memory cell. Thus, the proposed concept is promising to storage the messages in a memory cell beyond four-bit.

Silicon carbide (SiC) is one of the hardest known materials and is also, by good fortune, a wide bandgap semiconductor. While the application of SiC for high-temperature and high-power electronics is fairly well known, its utility as a highly robust, chemically-inert material for microelectrical mechanical systems (MEMS) is only beginning to be well recognized. SiC can be grown on both native SiC substrates or on Si using heteroepitaxial growth methods which affords the possibility to use Si micromachining methods to fabricate advanced SiC MEMS devices. The control of film stress in heteroepitaxial silicon carbide films grown on polysilicon-on-oxide substrates has been investigated. It is known that the size and structure of grains within polycrystalline films play an important role in determining the magnitude and type of stress present in a film, i.e. tensile or compressive. Silicon carbide grown on LPCVD polysilicon seed-films exhibited a highly-textured grain structure and displayed either a positive or negative stress gradient depending on the initial thickness of the polysilicon seed-layer. In addition a high-quality (111) oriented 3C-SiC on (111)Si heteroepitaxial process has been developed and is reported. SiC MEMS structures, both polycrystalline (i.e., poly-3C-SiC) and monocrystalline (i.e., 3C-SiC) were realized using micromachining methods. These structures were used to extract the stress properties of the films, with a particular focus on separating the gradient and uniform stress components.

No description available.

Design and analysis of polysilicon and single crystal silicon gyroscopes have been carried out. Variations in suspension design have been explored. Designs that utilize in-plane and out-of-plane sensing are studied. Damping plays an important role in determining the sense response. Reduction in damping directly affects sensor performance. The various damping mechanisms that are prevalent in gyroscopes are studied. Perforations on the proof mass are observed to significantly reduce the damping in the device when operated in air. The effects of perforation geometry and density have been analyzed. The analysis results show that there is a two orders of magnitude reduction in damping of thick gyroscope structures with optimized perforation design. Equivalent circuit lumped parameter models have been developed to analyze gyroscope performance. The simulation results of these models have been compared with results obtained from SABER, a MEMS specific system level design tool from Coventor-ware. The lumped parameter models are observed to produce faster simulation results with an accuracy comparable to that of Coventorware Three gyroscopes specific to the PolyMUMPS fabrication process have been designed and their performance analyzed. Two of the designs sense motion out-of-plane and the other senses motion in-plane. Results of the simulation show that for a given damping, the gyro design with in-plane modes gives a resolution of 4◦/s. The out-of-plane gyroscopes have two variations in suspension. The hammock suspension resolves a rate of 25◦/s in a 200 Hz bandwidth while the design with folded beam suspension resolves a rate of 2◦/s in a 12 Hz bandwidth. A single crystal silicon in-plane gyroscope has been designed with vertical electrodes to sense Coriolis motion. This design gives an order of magnitude higher capacitance change for a given rotation in comparison to conventional comb-finger design. The effects of process induced residual stress on the characteristic frequencies of the polysilicon gyroscopes are also studied. The in-plane gyroscope is found to be robust to stress variations. Analysis results indicate that the tuning fork gyroscope with the hammock suspension is the most susceptible to compressive residual stress, with a significant drop in sensitivity at high stress values.

No description available.

Apresentamos neste trabalho um estudo do efeito da depleção do silício policristalino e da corrente de tunelamento em dispositivos com óxidos de porta finos. Utilizamos curvas características da capacitância em função da tensão de porta (C-V), para analisar a degradação causada por estes efeitos.Quanto ao efeito da depleção do silício policristalino a capacitância total na região de inversão apresenta uma redução conforme a concentração de dopantes do silício policristalino diminui. Este efeito foi observado em curvas C-V tanto de alta como de baixa freqüência, sendo esta última mais afetada. A corrente de tunelamento através do óxido de porta apresentou uma influência na largura da região de depleção no silício, que aumentou devido ao tunelamento de portadores do substrato. Como resultado, uma diminuição na capacitância do silício foi observada, fazendo a curva C-V diminuir na região de inversão. Quando considerado o efeito de depleção no silício policristalino junto com o efeito do tunelamento, observou-se que na região da porta houve um excesso de portadores, causando uma diminuição na região de depleção do silício policristalino. Neste caso a curva C-V sofreu uma maior redução, tornando-se difícil separar os dois efeitos. A curva C-V de baixa freqüência foi a mais atingida, pois como os portadores tem tempo de resposta, pode-se observar a influência da corrente de tunelamento nas cargas de inversão. Apresentamos ainda um novo método para a determinação da concentração de dopantes no substrato e no silício policristalino, através de curvas C-V de alta freqüência. Simulações numéricas bidimensionais e medidas experimentais foram utilizadas para validação do método. Os resultados obtidos indicam que o método proposto apresenta um grande potencial, tendo como principal vantagem a simplicidade de aplicação. / In this work we present the study of polysilicon depletion and the gate tunneling current effects in thin-gate oxide devices. Characteristic curves of capacitance as a function of the gate voltage (C-V) were used to analyze the degradation caused for these effects. Regarding the poly depletion effect, a reduction of the total capacitance in the inversion region was verified as the polysilicon doping concentration decreases. This effect was observed in C-V curves in high and low frequency, being the last one more affected. The gate tunneling current presented an influence on the width of the depletion silicon region, which increased due to the carriers tunneling from the substrate. As a result, a reduction in the silicon capacitance was observed, causing the C-V curve reduction in the inversion region. When the polysilicon depletion effect is considered together with the tunneling effect, it was observed that there is a carriers excess in the gate region, causing a reduction of the polysilicon depletion region width. In this case, the C-V curve suffered a larger reduction, making difficult to separate both effects. The most affected characteristic was the C-V curve at low frequency, due to existence of the carrier response time that allows observing the influence of the tunneling current in inversion charges. A new method for the determination of the doping concentration of substrate and polysilicon was also presented, through C-V curves at high frequency. Two-dimensional simulations and experimental measurements were used to validate the method. The obtained results indicate that the propose method present a higher potential, having as principal advantage the simplicity of application.

Apresentamos neste trabalho um estudo do efeito da depleção do silício policristalino e da corrente de tunelamento em dispositivos com óxidos de porta finos. Utilizamos curvas características da capacitância em função da tensão de porta (C-V), para analisar a degradação causada por estes efeitos.Quanto ao efeito da depleção do silício policristalino a capacitância total na região de inversão apresenta uma redução conforme a concentração de dopantes do silício policristalino diminui. Este efeito foi observado em curvas C-V tanto de alta como de baixa freqüência, sendo esta última mais afetada. A corrente de tunelamento através do óxido de porta apresentou uma influência na largura da região de depleção no silício, que aumentou devido ao tunelamento de portadores do substrato. Como resultado, uma diminuição na capacitância do silício foi observada, fazendo a curva C-V diminuir na região de inversão. Quando considerado o efeito de depleção no silício policristalino junto com o efeito do tunelamento, observou-se que na região da porta houve um excesso de portadores, causando uma diminuição na região de depleção do silício policristalino. Neste caso a curva C-V sofreu uma maior redução, tornando-se difícil separar os dois efeitos. A curva C-V de baixa freqüência foi a mais atingida, pois como os portadores tem tempo de resposta, pode-se observar a influência da corrente de tunelamento nas cargas de inversão. Apresentamos ainda um novo método para a determinação da concentração de dopantes no substrato e no silício policristalino, através de curvas C-V de alta freqüência. Simulações numéricas bidimensionais e medidas experimentais foram utilizadas para validação do método. Os resultados obtidos indicam que o método proposto apresenta um grande potencial, tendo como principal vantagem a simplicidade de aplicação. / In this work we present the study of polysilicon depletion and the gate tunneling current effects in thin-gate oxide devices. Characteristic curves of capacitance as a function of the gate voltage (C-V) were used to analyze the degradation caused for these effects. Regarding the poly depletion effect, a reduction of the total capacitance in the inversion region was verified as the polysilicon doping concentration decreases. This effect was observed in C-V curves in high and low frequency, being the last one more affected. The gate tunneling current presented an influence on the width of the depletion silicon region, which increased due to the carriers tunneling from the substrate. As a result, a reduction in the silicon capacitance was observed, causing the C-V curve reduction in the inversion region. When the polysilicon depletion effect is considered together with the tunneling effect, it was observed that there is a carriers excess in the gate region, causing a reduction of the polysilicon depletion region width. In this case, the C-V curve suffered a larger reduction, making difficult to separate both effects. The most affected characteristic was the C-V curve at low frequency, due to existence of the carrier response time that allows observing the influence of the tunneling current in inversion charges. A new method for the determination of the doping concentration of substrate and polysilicon was also presented, through C-V curves at high frequency. Two-dimensional simulations and experimental measurements were used to validate the method. The obtained results indicate that the propose method present a higher potential, having as principal advantage the simplicity of application.

MEMS microphones have been a research topic for the last two and half decades. The state-of-the-art comprises surface mount MEMS microphones in laptops, mobile phones and tablets, etc. The popularity and the commercial success of MEMS microphones is largely due to the steep cost reduction in manufacturing afforded by the mass scale production with microfabrication technology. The current MEMS microphones are de-signed along the lines of traditional microphones that use capacitive transduction with or without permanent charge (electret type microphones use permanent charge of their sensor element). These microphones offer high sensitivity, stability and reasonably at frequency response while reducing the overall size and energy consumption by exploiting MEMS technology. Conceptually, microphones are simple transducers that use a membrane or diaphragm as a mechanical structure which deflects elastically in response to the incident acoustic pressure. This dynamic deflection is converted into an electrical signal using an appropriate transduction technique. The most popular transduction technique used for this application is capacitive, where an elastic diaphragm forms one of the two parallel plates of a capacitor, the fixed substrate or the base plate being the other one. Thus, there are basically two main elements in a microphone { the elastic membrane as a mechanical element, and the transduction technique as the electrical element. In this thesis, we propose and study novel design for both these elements. In the mechanical element, we propose a simple topological change by introducing slits in the membrane along its periphery to enhance the mechanical sensitivity. This simple change, however, has significant impact on the microphone design, performance and its eventual cost. Introduction of slits in the membrane makes the geometry of the structural element non-trivial for response analysis. We devote considerable effort in devising appropriate modeling techniques for deriving lumped parameters that are then used for simulating the system response. For transduction, we propose and study an FET (Field Effect Transistor) coupled micro-phone design where the elastic diaphragm is used as the moving (suspended) gate of an FET and the gate deflection modulated drain current is used in the subthreshold regime of operation as the output signal of the microphone. This design is explored in detail with respect to various design parameters in order to enhance the electrical sensitivity. Both proposed changes in the microphone design are motivated by the possibilities that the microfabrication technology offers. In fact, the design proposed here requires further developments in MEMS technology for reliably creating gaps of 50-100 nm between the substrate and a large 2D structure of the order of a few hundred microns in diameter. In the First part of the thesis, we present detailed simulations of acoustic and squeeze lm domain to understand the effect slits could bring upon the behaviour of the device as a microphone. Since the geometry is nontrivial, we resort to Finite element simulations using commercial packages such as COMSOL Multiphysics and ANSYS in the structural, acoustic and Fluid-structure domains to analyze the behaviour of a microphone which has top plate with nontrivial geometry. On the simulated Finite element data, we conduct low and high frequency limit analysis to extract expressions for the lumped parameters. This technique is well known in acoustics. We borrow this technique of curve Fitting from the acoustics domain and apply it in modified form into the squeeze lm domain. The dynamic behaviour of the entire device is then simulated using the extracted parameters. This helps to simulate the microphone behaviour either as a receiver or as a transmitter. The designed device is fabricated using MEMSCAP PolyMUMPS process (a foundry Polysilicon surface micromachining process). We conduct vibrometer (electrostatic ex-citation) and acoustic characterization. We also study the feasibility of a microphone with slits and the issues involved. The effect of the two dissipation modes (acoustic and squeeze lm ) are quantified with the experimentally determined quality factor. The experimentally measured values are: Resonance is 488 kHz (experimentally determined), low frequency roll-off is 796 Hz (theoretical value) and is 780 Hz as obtained by electrical characterization. The first part of this thesis focusses on developing a comprehensive understanding of the effect of slits on the performance of a MEMS microphone. The presence of slits near the circumference of the clamped plate cause reduction in its rigidity. This leads to an increase in the sensitivity of the device. Slits also cause pressure equalization between the top and bottom of the diaphragm if the incoming sound is at relatively low frequencies. At this frequency, also known as the lower cutoff frequency, the microphone's response starts dropping. The presence of slits also changes the radiation impedance of the plate as well as the squeeze lm damping below the plate. The useful bandwidth of the microphone changes as a consequence. The cavity formed between the top plate and the bottom fixed substrate increases the stiffness of the device significantly due to compression of the trapped air. This effect is more pronounced here because unlike the existing capacitive MEMS microphones, there is no backchamber in the device fabricated here. In the second part of the thesis, we present a novel subthreshold biased FET based MEMS microphone. This biasing of the transistor in the subthreshold region (also called as the OFF-region) offers higher sensitivity as compared to the above threshold region (also called as the ON-region) biasing. This is due to the exponentially varying current with change in the bias voltage in the OFF-region as compared to the quadratic variation in the ON-region. Detailed simulations are done to predict the behaviour of the device. A lumped parameter model of the mechanical domain is coupled with the drain current equations to predict the device behaviour in response to the deflection of the moving gate. From the simulations, we predict that the proposed biasing offers a device sensitive to even sub-nanometer deflection of the flexible gate. As a proof of concept, we fabricate fixed-fixed beams which utilize CMOS-MEMS fabrication. The process involves six lithography steps which involve two CMOS and the remaining MEMS fabrication. The fabricated beams are mechanically characterized for resonance. Further, we carry out electrical characterization for I-V (current-voltage) characteristics. The second part of the thesis focusses on a novel biasing method which circumvents the need of signal conditioning circuitry needed in a capacitive based transduction due to inbuilt amplification. Extensive simulations with equivalent circuit has been carried out to determine the increased sensitivity and the role of various design variables.

The present work is dedicated to the development of high performance integrated circuits for wireless communications, by acting of three different levels: technologies, devices, and circuits. Silicon-on-Insulator (SOI) CMOS technology is used in the frame of this work. Micromachining technologies are also investigated for the fabrication of three-dimensional tunable capacitors. The reliability of micromachined thin-film devices is improved by the coating of silanes in both liquid- and vapor-phases. Since in telecommunication applications, distortion is responsible for the generation of spurious frequency bands, the linearity behavior of different SOI transistors is analyzed. The validity range of the existing low-frequency nonlinear characterization methods is discussed. New simple techniques valid at both low- and high-frequencies, are provided, based on the integral function method and on the Volterra series. Finally, the design of a crucial nonlinear circuit, the voltage-controlled oscillator, is introduced. The describing function formalism is used to evaluate the oscillation amplitude and is embedded in a design methodology. The frequency tuning by SOI varactors is analyzed in both small- and large-signal regimes.