In a sensor monitoring embedded computing environment, the data from a sensor is an event that triggers the execution of an application. A sensor node consists of multiple sensors and a general purpose processor that handles the multiple events by deploying an event-driven software model. The software overheads of the general purpose processors results in energy inefficiency. What is needed is a class of special purpose processing elements which are more energy efficient for the purpose of computation. In the past, special purpose microcontrollers have been designed which are energy efficient for the targeted application space. However, reuse of the same design techniques is not feasible for other application domains. Therefore, this thesis presents a power-aware dataflow processor architecture targeted for the electronic textile computing space. The processor architecture has no instructions, and handles multiple events inherently without deploying software methods. This thesis also shows that the power-aware implementation reduces the overall static power consumption. / Master of Science

Degree awarded (2004): DScCS, Computer Science, George Washington University / A common practice to save power and energy in embedded systems is to "put to sleep" or disable parts of the hardware. The memory system consumes a significant portion of the energy budget of the overall system, so it is a natural target for energy optimization techniques. The principle of software locality makes the memory subsystem an even better choice, since all memory blocks but the ones immediately required can be disabled at any given time. This opportunity is the motivation for developing energy optimization techniques to dynamically and selectively control the power state of the different parts of the memory system. This dissertation develops a set of algorithms and techniques that can be organized into a hardware/software co-development tool to help designers apply the selective powering of memory blocks to minimize energy consumption. In data driven embedded systems, most of the data memory is used either by global static variables or by dynamic variables. Although techniques already exist for energy-aware allocation of global static arrays under certain constraints, very little work has focused on dynamic variables, which are actually more important to event driven/data driven embedded systems than their static counterparts. This dissertation addresses this gap, and extends and consolidates previous allocation techniques in a unique framework. A formal model for memory energy optimization for dynamic and global static variables and efficient algorithms for energy aware allocation of variables to memory are presented. Dependencies between generic code and data are uncovered, and this information is exploited to fine-tune a system. A framework is presented for retrieving this profile information which is then used to design energy aware allocation algorithms for dynamic variables, including heuristics for segmentation and control of the memory heap. By working at the assembly code level, these techniques can be integrated into any compiler regardless of the source language. The proposed techniques were implemented and tested against data intensive benchmarks, and experimental results indicate significant savings of up to 50% in the memory system energy consumption. / Advisory Committee: Professor Bhagirath Narahari, Professor Hyoeong-Ah Choi (Chair), Professor Rahul Simha, Professor Shmuel Rotenstreich, Professor Can E. Korman, Dr. Yul Williams

Au cours des dernières années, le nombre de systèmes informatiques n'a pas cesser d'augmenter. Les centres de données sont peu à peu devenus des équipements hautement demandés et font partie des plus consommateurs en énergie. L'utilisation des centres de données se partage entre le calcul intensif et les services web, aussi appelés informatique en nuage. La rapidité de calcul est primordiale pour le calcul intensif, mais pour les autres services ce paramètre peut varier selon les accords signés sur la qualité de service. Certains centres de données sont dits hybrides car ils combinent plusieurs types de services. Toutes ces infrastructures sont extrêmement énergivores. Dans ce présent manuscrit nous étudions les modèles de consommation énergétiques des systèmes informatiques. De tels modèles permettent une meilleure compréhension des serveurs informatiques et de leur façon de consommer l'énergie. Ils représentent donc un premier pas vers une meilleure gestion de ces systèmes, que ce soit pour faire des économies d'énergie ou pour facturer l'électricité à la charge des utilisateurs finaux. Les politiques de gestion et de contrôle de l'énergie comportent de nombreuses limites. En effet, la plupart des algorithmes d'ordonnancement sensibles à l'énergie utilisent des modèles de consommation restreints qui renferment un certain nombre de problèmes ouverts. De précédents travaux dans le domaine suggèrent d'utiliser les informations de contrôle fournies par le système informatique lui-même pour surveiller la consommation énergétique des applications. Néanmoins, ces modèles sont soit trop dépendants du type d'application, soit manquent de précision. Ce manuscrit présente des techniques permettant d'améliorer la précision des modèles de puissance en abordant des problèmes à plusieurs niveaux: depuis l'acquisition des mesures de puissance jusqu'à la définition d'une charge de travail générique permettant de créer un modèle lui aussi générique, c'est-à-dire qui pourra être utilisé pour des charges de travail hétérogènes. Pour atteindre un tel but, nous proposons d'utiliser des techniques d'apprentissage automatique.Les modèles d'apprentissage automatique sont facilement adaptables à l'architecture et sont le cœur de cette recherche. Ces travaux évaluent l'utilisation des réseaux de neurones artificiels et la régression linéaire comme technique d'apprentissage automatique pour faire de la modélisation statistique non linéaire. De tels modèles sont créés par une approche orientée données afin de pouvoir adapter les paramètres en fonction des informations collectées pendant l'exécution de charges de travail synthétiques. L'utilisation des techniques d'apprentissage automatique a pour but d'atteindre des estimateurs de très haute précision à la fois au niveau application et au niveau système. La méthodologie proposée est indépendante de l'architecture cible et peut facilement être reproductible quel que soit l'environnement. Les résultats montrent que l'utilisation de réseaux de neurones artificiels permet de créer des estimations très précises. Cependant, en raison de contraintes de modélisation, cette technique n'est pas applicable au niveau processus. Pour ce dernier, des modèles prédéfinis doivent être calibrés afin d'atteindre de bons résultats. / The number of computing systems is continuously increasing during the last years. The popularity of data centers turned them into one of the most power demanding facilities. The use of data centers is divided into high performance computing (HPC) and Internet services, or Clouds. Computing speed is crucial in HPC environments, while on Cloud systems it may vary according to their service-level agreements. Some data centers even propose hybrid environments, all of them are energy hungry. The present work is a study on power models for computing systems. These models allow a better understanding of the energy consumption of computers, and can be used as a first step towards better monitoring and management policies of such systems either to enhance their energy savings, or to account the energy to charge end-users. Energy management and control policies are subject to many limitations. Most energy-aware scheduling algorithms use restricted power models which have a number of open problems. Previous works in power modeling of computing systems proposed the use of system information to monitor the power consumption of applications. However, these models are either too specific for a given kind of application, or they lack of accuracy. This report presents techniques to enhance the accuracy of power models by tackling the issues since the measurements acquisition until the definition of a generic workload to enable the creation of a generic model, i.e. a model that can be used for heterogeneous workloads. To achieve such models, the use of machine learning techniques is proposed. Machine learning models are architecture adaptive and are used as the core of this research. More specifically, this work evaluates the use of artificial neural networks (ANN) and linear regression (LR) as machine learning techniques to perform non-linear statistical modeling.Such models are created through a data-driven approach, enabling adaptation of their parameters based on the information collected while running synthetic workloads. The use of machine learning techniques intends to achieve high accuracy application- and system-level estimators. The proposed methodology is architecture independent and can be easily reproduced in new environments.The results show that the use of artificial neural networks enables the creation of high accurate estimators. However, it cannot be applied at the process-level due to modeling constraints. For such case, predefined models can be calibrated to achieve fair results.% The use of process-level models enables the estimation of virtual machines' power consumption that can be used for Cloud provisioning.

Over the past few decades, we have been enjoying tremendous benefits thanks to the revolutionary advancement of computing systems, driven mainly by the remarkable semiconductor technology scaling and the increasingly complicated processor architecture. However, the exponentially increased transistor density has directly led to exponentially increased power consumption and dramatically elevated system temperature, which not only adversely impacts the system's cost, performance and reliability, but also increases the leakage and thus the overall power consumption. Today, the power and thermal issues have posed enormous challenges and threaten to slow down the continuous evolvement of computer technology. Effective power/thermal-aware design techniques are urgently demanded, at all design abstraction levels, from the circuit-level, the logic-level, to the architectural-level and the system-level. In this dissertation, we present our research efforts to employ real-time scheduling techniques to solve the resource-constrained power/thermal-aware, design-optimization problems. In our research, we developed a set of simple yet accurate system-level models to capture the processor's thermal dynamic as well as the interdependency of leakage power consumption, temperature, and supply voltage. Based on these models, we investigated the fundamental principles in power/thermal-aware scheduling, and developed real-time scheduling techniques targeting at a variety of design objectives, including peak temperature minimization, overall energy reduction, and performance maximization. The novelty of this work is that we integrate the cutting-edge research on power and thermal at the circuit and architectural-level into a set of accurate yet simplified system-level models, and are able to conduct system-level analysis and design based on these models. The theoretical study in this work serves as a solid foundation for the guidance of the power/thermal-aware scheduling algorithms development in practical computing systems.

Wireless network devices, especially in ad hoc networks, are typically battery-powered. The growing need for energy efficiency in wireless networks, in general, and in mobile ad hoc networks (MANETs), in particular, calls for power enhancement features. The goal of this dissertation is to extend network lifetime by improving energy utilization in MANET routing. We utilize the ability of wireless network interface cards to dynamically change their transmission power, as well as the ability of wireless devices to read the remaining battery energy of the device to create a table of what we term "reluctance values," which the device uses to determine how to route packets. Choosing routes with lower reluctance values, on average and with time, leads to better utilization of the energy resources of the devices in the network. Our power-aware scheme can be applied to both reactive and proactive MANET routing protocols. As examples and to evaluate performance, the technique has been applied to the Dynamic Source Routing (DSR) protocol, a reactive routing protocol, and the Optimized Link State Routing (OLSR) protocol, a proactive routing protocol. Simulations have been carried out on large static and mobile networks. Results show improvements in network lifetime in static and certain mobile scenarios. Results also show better distribution of residual node energies at the end of simulations, which means that the scheme is balancing energy load more evenly across network nodes than the unmodified versions of DSR and OLSR. Average change in energy over time in the unmodified protocols show a steady increase with time, while the power-aware protocols show an increase in the beginning, then it levels for sometime before it starts to decrease. The power-aware scheme shows improvements in static and in coordinated mobility scenarios. In random mobility the power-aware protocols show no advantage over the unmodified protocols. / Ph. D.

Demand response is one of the critical technologies necessary for allowing large-scale penetration of intermittent renewable energy sources in the electric grid. Data centers are especially attractive candidates for providing flexible, real-time demand response services to the grid because they are capable of fast power ramp-rates, large dynamic range, and finely-controllable power consumption. This thesis makes a contribution toward implementing load shaping with server clusters through a detailed experimental investigation of three broadly-applicable datacenter workload scenarios. We experimentally demonstrate the eminent feasibility of datacenter demand response with a distributed video transcoding application and a simple distributed power controller. We also show that while some software power capping interfaces performed better than others, all the interfaces we investigated had the high dynamic range and low power variance required to achieve high quality power tracking. Our next investigation presents an empirical performance evaluation of algorithms that replace arithmetic operations with low-level bit operations for power-aware Big Data processing. Specifically, we compare two different data structures in terms of execution time and power efficiency: (a) a baseline design using arrays, and (b) a design using bit-slice indexing (BSI) and distributed BSI arithmetic. Across three different datasets and three popular queries, we show that the bit-slicing queries consistently outperform the array algorithm in both power efficiency and execution time. In the context of datacenter power shaping, this performance optimization enables additional power flexibility -- achieving the same or greater performance than the baseline approach, even under power constraints. The investigation of read-optimized index queries leads up to an experimental investigation of the tradeoffs among power constraint, query freshness, and update aggregation size in a dynamic big data environment. We compare several update strategies, presenting a bitmap update optimization that allows improved performance over both a baseline approach and an existing state-of-the-art update strategy. Performing this investigation in the context of load shaping, we show that read-only range queries can be served without performance impact under power cap, and index updates can be tuned to provide a flexible base load. This thesis concludes with a brief discussion of control implementation and summary of our findings.

Computing systems are experiencing a significant evolution triggered by the convergence of multiple technologies including multicore processor architectures, expanding I/O capabilities (e.g., storage and wireless communication), and virtualization solutions. The integration of these technologies has been driven by the need to deliver performance and functionality for applications being developed in emerging mobile and enterprise systems. These accomplishments, though, have come at the cost of increased power and thermal signatures of computing platforms. In response to the resulting power issues, power centric policies have been deployed across all layers of the stack including platform hardware, operating systems, application middleware, and virtualization components. Effective active power management requires that these independent layers or components behave constructively to attain globally desirable benefits. Two choices are (1) to tightly integrate different policies using negotiated management decisions, and (2) to coordinate their use based on the localized policy decisions that are already part of modern computer architectures and software systems. Recognizing the realities of (2), the goal of this thesis is to identify, define, and evaluate novel system-level coordination mechanisms between diverse management components that exist across system layers. The end goal of these mechanisms, then, is to enable synergistic behaviors between management entities, across different levels of abstraction, and across different physical platforms to improve power management functionality. Contributions from this work include operating system level mechanisms that dynamically capture workload behavior thereby enabling power efficient scheduling, and system descriptor mechanisms that allow for improved workload allocation and resource management schemes. Finally, observing the strong need for coordination in managing virtualized systems due to the existence of multiple, independent system layers, a set of extensions to virtualization architectures for effectively coordinating VM management in datacenters are developed.

Heterogeneous processors intended for mobile devices are composed of a number of different CPU cores that enable the processor to optimize performance under strict power limits that vary over time. Design space exploration techniques can be used to discover a candidate set of potential cores that could be implemented on a heterogeneous processor. However, candidate sets contain far more cores than can feasibly be implemented. Heterogeneous processor composition therefore requires solutions to the selection problem and the evaluation problem. Cores must be selected from the candidate set, and these cores must be shown to be quantitatively superior to alternative selections. The qualitative criterion for a selection of cores is diversity. A diverse set of heterogeneous cores allows a processor to execute tasks with varying dynamic behaviors at a range of power and performance levels that are appropriate for conditions during runtime. This thesis presents a detailed description of the selection and evaluation problems, and establishes a theoretical framework for reasoning about the runtime behavior of power-limited, heterogeneous processors. The evaluation problem is specifically concerned with evaluating the collective attributes of selections of cores rather than evaluating the features of individual cores. A suite of metrics is defined to address the evaluation problem. The metrics quantify considerations that could otherwise only be evaluated subjectively. The selection problem is addressed with an iterative, diversity-preserving algorithm that emphasizes the flexibility available to programs at runtime. The algorithm includes facilities for guiding the selection process with information from an expert, when available. Three variations on the selection algorithm are defined. A thorough analysis of the proposed selection algorithm is presented using data from a large-scale simulation involving 33 benchmarks and 3000 core types. The three variations of the algorithm are compared to each other and to current, state-of-the-art selection techniques. The analysis serves as both an evaluation of the proposed algorithm as well as a case study of the metrics.

The parallel nature of process execution on chip multiprocessors (CMPs) has considerably boosted levels of application performance in the past decade. Generally, a certain number of computing resources are shared among the several cores of a CMP, such as shared last-level caches, shared-buses, and shared-memory. This ensures architectural simplicity while also boosting performance for multi-threaded applications. However, a consequence of sharing computing resources is that concurrently executing applications may suffer performance degradation if their collective resource requirements exceed the total amount of resources available. If resource allocation is not carefully considered, the potential performance gain from having multiple cores may be outweighed by the losses due to contention among processes for shared resources. Furthermore, CMPs with inbuilt dynamic voltage-frequency scaling (DVFS) may try to compensate for the performance loss by scaling to a higher frequency. For performance degradation due to shared-resource contention, this does not necessarily improve performance but guarantees a significant penalty on power consumption due to the quadratic relation of electrical power and voltage (P ∝ V^{2}*f).

Massive parallelism combined with complex memory hierarchies and heterogeneity in high-performance computing (HPC) systems form a barrier to efficient application and architecture design. The performance achievements of the past must continue over the next decade to address the needs of scientific simulations. However, building an exascale system by 2022 that uses less than 20 megawatts will require significant innovations in power and performance efficiency. A key limitation of past approaches is a lack of power-performance policies allowing users to quantitatively bound the effects of power management on the performance of their applications and systems. Existing controllers and predictors use policies fixed by a knowledgeable user to opportunistically save energy and minimize performance impact. While the qualitative effects are often good and the aggressiveness of a controller can be tuned to try to save more or less energy, the quantitative effects of tuning and setting opportunistic policies on performance and power are unknown. In other words, the controller will save energy and minimize performance loss in many cases but we have little understanding of the quantitative effects of controller tuning. This makes setting power-performance policies a manual trial and error process for domain experts and a black art for practitioners. To improve upon past approaches to high-performance power management, we need to quantitatively understand the effects of power and performance at scale. In this work, I have developed theories and techniques to quantitatively understand the relationship between power and performance for high performance systems at scale. For instance, our system-level, iso-energy-efficiency model analyzes, evaluates and predicts the performance and energy use of data intensive parallel applications on multi-core systems. This model allows users to study the effects of machine and application dependent characteristics on system energy efficiency. Furthermore, this model helps users isolate root causes of energy or performance inefficiencies and develop strategies for scaling systems to maintain or improve efficiency.  I have also developed methodologies which can be extended and applied to model modern heterogeneous architectures such as GPU-based clusters to improve their efficiency at scale. / Ph. D.