Energy consumption is one of the most constrained requirements for the development and implementation of wireless sensor networks. Many design aspects affect energy consumption, ranging from the hardware components, operations of the sensors, the communication protocols, the application algorithms, duty cycles and others. Efficient simulation tool can be used to estimate the contribution to energy consumption of all of these factors, and significantly decrease the efforts and time spent to choose the right solution that fits best to a particular application. In this work we present design space exploration methodology for ultra low power embedded systems and wireless sensor networks. The methodology takes inspiration from Platform Based Design (PBD) paradigm and defines separate abstraction layers for all system aspects that directly contribute power consumption of target applications. To support presented methodology we built a SystemC-based discrete event simulation framework, called “PASES”, that provides power-aware simulation and analysis of wireless sensor networks and sensor nodes. Its modular architecture allows flexible, extensible and rapid modeling of custom HW platforms, SW application models, communication protocols, energy sources, environment dynamics and nodes mobility. Based on the feedback gained from PASES, the optimal and energy-efficient solution for the specific project of interest can be selected. The proposed approach improves state-of-the-art by providing fast and reliable power-aware system-level exploration for a wide range of custom applications

Multicore architectures impose great pressure on resource management. The exploration spaces available for resource management increase explosively, especially for large-scale high end computing systems. The availability of abundant parallelism causes scalability concerns at all levels. Multicore architectures also impose pressure on power management. Growth in the number of cores causes continuous growth in power. In this dissertation, we introduce methods and techniques to enable scalable and energy efficient execution of parallel applications on multicore architectures. We study strategies and methodologies that combine DCT and DVFS for the hybrid MPI/OpenMP programming model. Our algorithms yield substantial energy saving (8.74% on average and up to 13.8%) with either negligible performance loss or performance gain (up to 7.5%). To save additional energy for high-end computing systems, we propose a power-aware MPI task aggregation framework. The framework predicts the performance effect of task aggregation in both computation and communication phases and its impact in terms of execution time and energy of MPI programs. Our framework provides accurate predictions that lead to substantial energy saving through aggregation (64.87% on average and up to 70.03%) with tolerable performance loss (under 5%). As we aggregate multiple MPI tasks within the same node, we have the scalability concern of memory registration for high performance networking. We propose a new memory registration/deregistration strategy to reduce registered memory on multicore architectures with helper threads. We investigate design polices and performance implications of the helper thread approach. Our method efficiently reduces registered memory (23.62% on average and up to 49.39%) and avoids memory registration/deregistration costs for reused communication memory. Our system enables the execution of application input sets that could not run to the completion with the memory registration limitation. / Ph. D.

The scalability of parallel applications executing on multithreaded and multicore multiprocessors is often quite limited due to large degrees of contention over shared resources on these systems. In fact, negative scalability frequently occurs such that a non-negligable performance loss is observed through the use of more processors and cores. In this dissertation, we present a prediction model for identifying efficient operating points of concurrency in multithreaded scientific applications in terms of both performance as a primary objective and power secondarily. We also present a runtime system that uses live analysis of hardware event rates through the prediction model to optimize applications dynamically. We discuss a dynamic, phase-aware performance prediction model (DPAPP), which combines statistical learning techniques, including multivariate linear regression and artificial neural networks, with runtime analysis of data collected from hardware event counters to locate optimal operating points of concurrency. We find that the scalability model achieves accuracy approaching 95%, sufficiently accurate to identify improved concurrency levels and thread placements from within real parallel scientific applications. Using DPAPP, we develop a prediction-driven runtime optimization scheme, called ACTOR, which throttles concurrency so that power consumption can be reduced and performance can be set at the knee of the scalability curve of each parallel execution phase in an application. ACTOR successfully identifies and exploits program phases where limited scalability results in a performance loss through the use of more processing elements, providing simultaneous reductions in execution time by 5%-18% and power consumption by 0%-11% across a variety of parallel applications and architectures. Further, we extend DPAPP and ACTOR to include support for runtime adaptation of DVFS, allowing for the synergistic exploitation of concurrency throttling and DVFS from within a single, autonomically-acting library, providing improved energy-efficiency compared to either approach in isolation. / Ph. D.

Power has become a primary concern for HPC systems. Dynamic voltage and frequency scaling (DVFS) and dynamic concurrency throttling (DCT) are two software tools (or knobs) for reducing the dynamic power consumption of HPC systems. To date, few works have considered the synergistic integration of DVFS and DCT in performance-constrained systems, and, to the best of our knowledge, no prior research has developed application-aware simultaneous DVFS and DCT controllers in real systems and parallel programming frameworks. We present a multi-dimensional, online performance prediction framework, which we deploy to address the problem of simultaneous runtime optimization of DVFS, DCT, and thread placement on multi-core systems. We present results from an implementation of the prediction framework in a runtime system linked to the Intel OpenMP runtime environment and running on a real dual-processor quad-core system as well as a dual-processor dual-core system. We show that the prediction framework derives near-optimal settings of the three power-aware program adaptation knobs that we consider. Our overall runtime optimization framework achieves significant reductions in energy (12.27% mean) and ED² (29.6% mean), through simultaneous power savings (3.9% mean) and performance improvements (10.3% mean). Our prediction and adaptation framework outperforms earlier solutions that adapt only DVFS or DCT, as well as one that sequentially applies DCT then DVFS. Further, our results indicate that prediction-based schemes for runtime adaptation compare favorably and typically improve upon heuristic search-based approaches in both performance and energy savings. / Master of Science

Green computing, an emerging field of research that seeks to reduce excess power consumption in high performance computing (HPC), is gaining popularity among researchers. Research in this field often relies on simulation or only uses a small cluster, typically 8 or 16 nodes, because of the lack of hardware support. In contrast, System G at Virginia Tech is a 2592 processor supercomputer equipped with power aware components suitable for large scale green computing research. DIRECT is a deterministic global optimization algorithm, implemented in the mathematical software package VTDIRECT95. This thesis explores the potential energy savings for the parallel implementation of DIRECT, called pVTdirect, when used with a large scale computational biology application, parameter estimation for a budding yeast cell cycle model, on System G. Two power aware approaches for pVTdirect are developed and compared against the CPUSPEED power saving system tool. The results show that knowledge of the parallel workload of the underlying application is beneficial for power management. / Master of Science

By 2004, microprocessor design focused on multicore scaling"increasing the number of cores per die in each generation "as the primary strategy for improving performance. These multicore processors typically equip multiple memory subsystems to improve data throughput. In addition, these systems employ heterogeneous processors such as GPUs and heterogeneous memories like non-volatile memory to improve performance, capacity, and energy efficiency. With the increasing volume of hardware resources and system complexity caused by heterogeneity, future systems will require intelligent ways to manage hardware resources. Early research to improve performance and energy efficiency on heterogeneous, multi-core, multi-memory systems focused on tuning a single primitive or at best a few primitives in the systems. The key limitation of past efforts is their lack of a holistic approach to resource management that balances the tradeoff between performance and energy consumption. In addition, the shift from simple, homogeneous systems to these heterogeneous, multicore, multi-memory systems requires in-depth understanding of efficient resource management for scalable execution, including new models that capture the interchange between performance and energy, smarter resource management strategies, and novel low-level performance/energy tuning primitives and runtime systems. Tuning an application to control available resources efficiently has become a daunting challenge; managing resources in automation is still a dark art since the tradeoffs among programming, energy, and performance remain insufficiently understood. In this dissertation, I have developed theories, models, and resource management techniques to enable energy-efficient execution of parallel applications through thread and data management in these heterogeneous multi-core, multi-memory systems. I study the effect of dynamic concurrent throttling on the performance and energy of multi-core, non-uniform memory access (NUMA) systems. I use critical path analysis to quantify memory contention in the NUMA memory system and determine thread mappings. In addition, I implement a runtime system that combines concurrent throttling and a novel thread mapping algorithm to manage thread resources and improve energy efficient execution in multi-core, NUMA systems. In addition, I propose an analytical model based on the queuing method that captures important factors in multi-core, multi-memory systems to quantify the tradeoff between performance and energy. The model considers the effect of these factors in a holistic fashion that provides a general view of performance and energy consumption in contemporary systems. Finally, I focus on resource management of future heterogeneous memory systems, which may combine two heterogeneous memories to scale out memory capacity while maintaining reasonable power use. I present a new memory controller design that combines the best aspects of two baseline heterogeneous page management policies to migrate data between two heterogeneous memories so as to optimize performance and energy. / Ph. D.

Ett centralt problem i strävan efter att minska energianvändningen i hushåll genom beteendeförändringar är att energi till stora delar är en osynlig produkt. Avhandlingen strävar efter att utveckla kunskap som kan bidra till mer hållbar utveckling genom att analysera tre företeelser som på ett konkret sätt synliggör energi och energirelaterat beteende: ett lokalt värmesystem, en s.k. Power Aware Cord och en dagboksmetod. Hur människor förstår sin energianvändning analyseras med hjälp av en modifierad version av den domesticeringsteori som utvecklats av Silverstone et al (1992). I centrum står paradoxen att de visualiserande företeelserna riskerar att själva osynliggöras genom att de domesticeras. Värmesystemet har haft en bristande funktion, vilket har varit den faktor som mest effektivt visualiserat systemet. Solfångarnas visuella dominans i områdets arkitektur har bidragit till att medvetandegöra solen som energikälla. Ett teknikrum och olika experter har också medvetandegjort själva värmesystemets existens. Såväl systemet som helhet som hushållens egen del i detta har visualiserats. Power Aware Cord liknar en vanlig grendosa, men den visar elanvändningen (effekten) hos den utrustning som kopplas till den. Energin visualiseras med hjälp av ett blått ljus i sladden vars intensitet anpassas efter watttalet som passerar genom sladden. Power Aware Cords styrka ligger i att den bidrar till att apparaters energianvändning visualiseras. Tidsdagboken visualiserar hushållsmedlemmarnas vardagliga aktiviteter på ett bredare plan än enbart i relation till energianvändning. Analysen visar att den redan osynliga resursen energi, som blivit än mer osynliggjort genom domesticering, kan avdomesticeras genom olika former för visualisering. Visualiseringsformerna riskerar dock att själva domesticeras. För att dessa ska ha varaktig effekt behövs strategier för att undvika detta. / One problem in promoting sustainable energy use is that energy is taken for granted. Energy as resource needs to be made visible. This dissertation aims to develop knowledge that can contribute to more sustainable development by analyzing different ways to visualize domestic energy systems. Three different forms of visualization are analyzed: a locally situated heating-system, the Power Aware Cord, and a diary method. How people understand their energy use is analyzed using a modified version of domestication theory as developed by Silverstone et al. (1992). Another focus is the paradox that forms of visualization themselves risk becoming invisible by virtue of being domesticated. The heating system still does not function as intended, and the non-functioning of the heating system has been the most effective means of visualizing the system. The solar collectors are visible and are a dominant element of the area’s architecture; this has helped visualize, make people aware of, and confer an understanding of the sun as an energy source. A technical control room and technicians have also helped visualize the existence of the heating system. The system as a whole, and the households’ own parts of it, has been visualized. The Power Aware Cord is the general shape of an extendable power strip, with the additional integration of voltage-measuring electronics and electroluminescent wire. This additional wire contains a phosphor layer that glows when an altering current is introduced. The cords’ strength lies in visualizing the household energy use of particular electrical devices. The time diary method visualizes the household members’ individual and inter-related ctivity patterns in a broader, more general way. The analysis shows that the already invisible resource energy, which has been made doubly invisible through domestication, can be de-domesticated through the domestication of forms of visualization. At the same time, the forms of visualization themselves risk being made invisible by being domesticated; for forms of visualization to have any lasting effect, strategies for avoiding this must be developed.

Aggressive scaling of nanoscale CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. The main contribution of this dissertation is the development of unified physical and high-level synthesis techniques for the design of ASICs with optimal chip temperatures and interconnect delays. Thermal issues are becoming a serious problem in high-performance VLSI circuits, adversely impacting performance, reliability, power consumption, and cooling costs. To address this, we present a temperature-aware behavioral synthesis (TABS) framework that combines power minimization with temperature-aware task scheduling, resource binding, and floorplanning. Compared to conventional low-power synthesis methods, our approach is effective in synthesizing circuits with lower chip temperatures and more uniform thermal distributions, with temperature reductions up to 23% when compared to low-power synthesis. We propose three techniques to address interconnect delays during high-level synthesis: (1) a simulated annealing (SA) based layout-aware high-level synthesis technique for 3-D integrated circuits, that tightly couples the synthesis tasks of resource binding and 3-D floorplanning. The proposed algorithm significantly outperforms a conventional synthesis flow that separates the binding and floorplanning steps, with improvements in the total wirelength by 29% and of the longest wirelength by 21%; (2) a floorplan-aware high-level synthesis technique that uses the topology of multi-terminal nets to improve interconnect delay estimates during resource binding. Experiments show that the use of accurate wire delay estimates during binding can reduce wire delays by as much as 49% in 70nm technology; (3) an iterative high-level design-space exploration engine that uses a priori stochastic wirelength estimates to guide binding decisions during high-level synthesis. The proposed approach offers a significant speed-up during design space exploration when compared to approaches that use traditional place-and-route to evaluate candidate solutions. Finally, we present a genetic algorithm (GA) based approach for high-level synthesis. We propose novel GA encoding, crossover, and mutation operators for the problem. The quality of the results generated by the GA are superior to those of several other techniques reported in the literature.

In this thesis, performance of the Contribution Reward Routing Protocol with Shapley Value (CAP-SV), a power-aware routing protocol for ad hoc networking is analyzed. Literature study on ad hoc network routing and ower-awareness is given. The overhead induced by the extra packets of the redirection mechanism of CAP-SV is formulized and the factors affecting this overhead are discussed. Then, the power consumption of CAP-SV is analytically analized using a linear power consumption model. It is shown that CAP-SV performs better than AODV regarding power consumption. The analysis validates the simulation results reported in the literature and provides general principles of how protocol and scenario parameters affect the performance.

One of the challenging issues for mobile ad hoc network (MANET) applications is data replication. Unreliable wireless communication, mobility of network participators and limited resource capacities of mobile devices make conventional replication techniques useless for MANETs. Frequent network divisions and unexpected disconnections should be handled. In this thesis work, a novel mobility and power aware, data interest based data replication strategy is presented. Main objective is to improve data accessibility among a mission critical mobility group. A clustering approach depending on mobility and data interest patterns similarities is introduced. The investigated replica allocation methodology takes care of data access frequency and data correlation values together with mobile nodes&rsquo / remaining energy and memory capacities. Performance of the proposed approach is analyzed in terms of data accessibility / cache hit ratio and traffic metrics. Improvements are observed by data interest based clustering in addition to mobility awareness over sole mobility aware clustering. Advantages of power aware replica allocation are demonstrated by experimental simulations.