Os sistemas produtivos (SPs) podem utilizar controladores programáveis (CPs) como dispositivos de realização do controle. Neste contexto, programas de controle executados por estes CPs podem ser desenvolvidos de forma que não estejam em conformidade com as especificações de projeto, o que poderá provocar o surgimento de erros funcionais associados à execução de tais programas de controle, erros estes que podem levar os SPs sob controle a um estado que poderá implicar em acidentes envolvendo equipamentos, pessoas e o meio-ambiente. Esta questão tem motivado o surgimento de diversas abordagens para identificar a existência de erros em programas de controle de CPs, de forma a permitir a correção destes erros e garantir, conseqüentemente, maior confiabilidade operacional. O presente trabalho tem por objetivo identificar a existência de erros em programas de controle baseados em LD (Ladder Diagram). Para isto, propõe-se um procedimento de desenvolvimento de modelos baseados em máquinas de estados finitos estendidas (MEFEs), que são gerados a partir do mapeamento de cada um dos rungs contidos no programa de controle que se deseja identificar erros. Uma vez desenvolvidos os modelos em MEFEs, torna-se possível a utilização de uma ferramenta computacional de verificação, própria para estabelecer se os modelos verificados satisfazem determinadas proposições estabelecidas em lógica temporal. Uma proposição em lógica temporal está relacionada a um estado específico do programa de controle modelado, sendo que o objetivo da verificação é o de estabelecer se a proposição estipulada é atendida ou não. Se um determinado estado específico for, por exemplo, um estado indesejado do programa de controle modelado, e este estado for possível de ser alcançado como resultado do processo de verificação realizado, isto impactará na não conformidade do programa de controle com as especificações comportamentais estipuladas na forma de proposição em lógica temporal, indicando haver, portanto, um erro neste programa de controle modelado. Palavras-chave: Controladores programáveis. Linguagem de programação LD. Modelagem e verificação de máquinas de estados finitos estendidas (MEFEs). / Productive systems (PS) can use programmable logic controllers (PLCs) as the devices of accomplishment of the control. In this context, control programs executed by these PLCs can be developed in a way so that they can be in non-conformity with the project specifications, and this fact may result in functional errors related to the control programs execution. These errors can take the PS under control to a state which can lead into accidents involving equipment, people and the environment. This fact has motivated the appearance of different approaches so as to identify the existence of these errors in PLC control programs so that they can be corrected and assure a greater operational reliability. This work aims at identifying the existence of errors in control programs based on Ladder Diagram (LD). In order to accomplish that, a modeling procedure that generates extended finite state machines (EFSMs) is proposed from the mapping of each one of the rungs in the control program whose errors are to be identified. Once the models based on EFSMs are developed it becomes possible to use a computational verification tool, specifically designed to determine if the verified models fulfill determined propositions established in temporal logic. A proposition in temporal logic is related to a specific state of the modeled control program and the objective of the verification is to establish whether the proposition is fulfilled or not. If a determined specific state, for example, is an unwanted state of the modeled control program and if this state is reachable as a result of the verification process, this will impact in the non-conformity of the control program with the behavior specifications established in a temporal logic proposition, indicating an error in this modeled control program.

Ao final desta pesquisa deseja-se que haja uma metodologia eficiente, cuja finalidade será auxiliar o usuário na transformação de modelos matemáticos e computacionais codificados para computadores sequenciais, em modelos paralelos otimizados para executarem em microcomputadores pessoais modernos, constituídos de CPU com múltiplos núcleos ou de híbridos (CPU + GPGPU) integrados no mesmo chip, com ou sem processadores gráficos (GPGPU) densamente paralelos instalados, mantendo a qualidade de seus resultados originais, com respeito à sua precisão numérica, mas com uma diminuição considerável no tempo de processamento. A emergência, em meados da década 2000, dessas novas arquiteturas de hardware elevou a capacidade de processamento dos microcomputadores pessoais aos patamares dos computadores de grande porte de apenas alguns anos atrás. Este trabalho de pesquisa apresenta duas metodologias, onde a primeira metodologia é composta de três partes e a segunda de duas partes. Somente a terceira parte da primeira metodologia é dependente de tecnologias de hardware. / At the end of this research project, an efficient methodology is expected with the purpose of assisting users in the processing of mathematical and computer models coded for sequential computers in parallel models that are optimized to run on modern personal computers, consisting of a CPU with multiple or hybrid (CPU + GPGPU) cores integrated into the same chip, with or without massively parallel graphics processors (GPGPU) installed. This will ensure the original quality of the results with respect to numerical accuracy, but with a considerable reduction in processing time. The emergence of these new hardware architectures in the mid-2000s increased the processing power of personal computers to the levels of mainframe computers from just a few years previously. This research work presents two methodologies, where the first methodology is composed of three parts and the second methodology is composed of two parts. Only the third part of the first methodology is dependent on hardware technologies.

Ao final desta pesquisa deseja-se que haja uma metodologia eficiente, cuja finalidade será auxiliar o usuário na transformação de modelos matemáticos e computacionais codificados para computadores sequenciais, em modelos paralelos otimizados para executarem em microcomputadores pessoais modernos, constituídos de CPU com múltiplos núcleos ou de híbridos (CPU + GPGPU) integrados no mesmo chip, com ou sem processadores gráficos (GPGPU) densamente paralelos instalados, mantendo a qualidade de seus resultados originais, com respeito à sua precisão numérica, mas com uma diminuição considerável no tempo de processamento. A emergência, em meados da década 2000, dessas novas arquiteturas de hardware elevou a capacidade de processamento dos microcomputadores pessoais aos patamares dos computadores de grande porte de apenas alguns anos atrás. Este trabalho de pesquisa apresenta duas metodologias, onde a primeira metodologia é composta de três partes e a segunda de duas partes. Somente a terceira parte da primeira metodologia é dependente de tecnologias de hardware. / At the end of this research project, an efficient methodology is expected with the purpose of assisting users in the processing of mathematical and computer models coded for sequential computers in parallel models that are optimized to run on modern personal computers, consisting of a CPU with multiple or hybrid (CPU + GPGPU) cores integrated into the same chip, with or without massively parallel graphics processors (GPGPU) installed. This will ensure the original quality of the results with respect to numerical accuracy, but with a considerable reduction in processing time. The emergence of these new hardware architectures in the mid-2000s increased the processing power of personal computers to the levels of mainframe computers from just a few years previously. This research work presents two methodologies, where the first methodology is composed of three parts and the second methodology is composed of two parts. Only the third part of the first methodology is dependent on hardware technologies.

Submitted by Silvana Teresinha Dornelles Studzinski (sstudzinski) on 2017-03-03T16:51:21Z No. of bitstreams: 1 Sandro José Ribeiro da Silva_.pdf: 1958508 bytes, checksum: 927c5b673859ca465e35998f946b5a64 (MD5) / Made available in DSpace on 2017-03-03T16:51:21Z (GMT). No. of bitstreams: 1 Sandro José Ribeiro da Silva_.pdf: 1958508 bytes, checksum: 927c5b673859ca465e35998f946b5a64 (MD5) Previous issue date: 2016-11-03 / Nenhuma / O desenvolvimento de habilidades de programação de sistemas computacionais é uma necessidade crescente, devido ao amplo uso de recursos computacionais nas mais diversas áreas. Ao mesmo tempo, é conhecida a deficiência existente quanto à quantidade de profissionais sendo graduados nesta área. Alguns estudos indicam dificuldades dos estudantes e ao mesmo tempo falta de metodologias adequadas como possíveis elementos contribuindo para este contexto, corroborando a necessidade de desenvolvimento de pesquisas sobre o aprendizado de linguagens de programação. Entre as possíveis soluções para este problema de motivação, o desenvolvimento de um ambiente gamificado como ferramenta de ensino para linguagens de programação vem sendo explorado em projetos de pesquisa e também em opções comerciais. Uma das deficiências observadas nestas inciativas é justamente a falta de suporte aos professores para acompanhamento da evolução dos alunos. Buscando atender esta necessidade, o presente trabalho propõe um ambiente de apoio ao ensino de lógica de programação cujo diferencial é a inclusão de recursos de análise do comportamento dos alunos, voltados para o apoio ao professor. Desta forma, o trabalho proposto alia aos jogos eletrônicos o monitoramento on-line de suas etapas, através do uso de técnicas de mineração de dados educacionais. Com base em um framework para Gamificação, foi definido e desenvolvido um ambiente Web para ensino da linguagem Lua, com aspectos de Gamificação e Mineração de Dados Educacionais. Este ambiente foi utilizado em avaliações com alunos do ensino técnico, tendo sido observados resultados promissores nos aspectos motivacionais. As avaliações envolvendo a identificação de vantagens geradas para os professores com uso dos dados sobre o comportamento dos alunos também foram positivas e indicam um bom potencial para esta abordagem. / The development of computer systems programming skills is a growing necessity, due to the wide use of computational resources in different areas. At the same time, it is known the deficiency with respect to the amount of professionals being graduated in this area. Some studies indicates difficulties of students and lack of adequate methodologies as possible elements contributing to this context, supporting the need to develop research on learning programming languages. As a possible solution to this problem of motivation, the development of a gamified environment as a teaching tool for programming languages is being explored in research projects and also commercial options. One of the deficiencies observed in these initiatives is precisely the lack of support to teachers to follow up of the evolution of students, which consists in one of the differentials of the proposed work. In this way, the work integrates to electronic games the online monitoring through the use of educational data mining techniques. Based on the framework for gamification, has been defined and developed a web environment to the Lua language teaching, with aspects of gamification and education data mining. This environment has already been tested preliminarily with technical education students, being observed promising results. A new stage of development and testing is foreseen to deepening the identification of advantages generated for teachers with the use data on the behavior of students.

<p>This project was held at London South Bank University in the UK, with corporation with staff from Linköping University in Sweden as Bachelor thesis.</p><p>This report will guide you through the used techniques in order to achieve a successful cooler/Fan project with a minimum budget and good energy saving methods.</p><p>The steps of setting the used software and components are supported with figures and diagrams. You will find full explanation of the used components and mathematics, in additional to a complete working code.</p>

<p>Over the last three decades, computer architects have been able to achieve an increase in performance for single processors by, e.g., increasing clock speed, introducing cache memories and using instruction level parallelism. However, because of power consumption and heat dissipation constraints, this trend is going to cease. In recent times, hardware engineers have instead moved to new chip architectures with multiple processor cores on a single chip. With multi-core processors, applications can complete more total work than with one core alone. To take advantage of multi-core processors, we have to develop parallel applications that assign tasks to different cores. On each core, pipeline, data and task parallelization can be used to achieve higher performance. Dataflow programming languages are attractive for achieving parallelism because of their high-level, machine-independent, implicitly parallel notation and because of their fine-grain parallelism. These features are essential for obtaining effective, scalable utilization of multi-core processors.</p><p>In this thesis work we have parallelized an existing audio codec - Adaptive Multi-Rate Wide Band (AMR-WB) - written in the C language for single core processor. The target platform is a multi-core AMR11 MP developer board. The final result of the efforts is a working AMR-WB encoder implemented in CAL and running in the OpenDF simulator. The C specification of the AMR-WB encoder was analysed with respect to dataflow and parallelism. The final implementation was developed in the CAL Actor Language, with the goal of exposing available parallelism - different dataflows - as well as removing unwanted data dependencies. Our thesis work discusses mapping techniques and guidelines that we followed and which can be used in any future work regarding mapping C based applications to CAL. We also propose solutions for some specific dependencies that were revealed in the AMR-WB encoder analysis and suggest further investigation of possible modifications to the encoder to enable more efficient implementation on a multi-core target system.</p>

When practicing secure programming, it is important to understand the restrictive influence programmed entities have on the propagation of authority in a program. To precisely model authority propagation in patterns of interacting entities, we present a new formalism Knowledge Behavior Models (KBM). To describe such patterns, we present a new domain specific declarative language SCOLL (Safe Collaboration Language), which semantics are expressed by means of KBMs. To calculate the solutions for the safety problems expressed in SCOLL, we have built SCOLLAR: a model checker and solver based on constraint logic programming. SCOLLAR not only indicates whether the safety requirements are guaranteed by the restricted behavior of the relied-upon entities, but also lists the different ways in which their behavior can be restricted to guarantee the safety properties without precluding their required functionality and (re-)usability. How the tool can help programmers to build reliable components that can safely interact with partially or completely untrusted components is shown in elaborate examples.

This project was held at London South Bank University in the UK, with corporation with staff from Linköping University in Sweden as Bachelor thesis. This report will guide you through the used techniques in order to achieve a successful cooler/Fan project with a minimum budget and good energy saving methods. The steps of setting the used software and components are supported with figures and diagrams. You will find full explanation of the used components and mathematics, in additional to a complete working code.

The intricate concepts of ad-hoc polymorphism and overloading permeate the field of programming languages despite their somewhat nebulous definitions. With the perspective afforded by the state of the art, object-oriented Fortress programming language, this thesis presents a contemporary account of ad-hoc polymorphism and overloading in theory and in practice. Common language constructs are reinterpreted with a new emphasis on overloading as a key facility. Furthermore, concrete problems with overloading in Fortress, encountered during the author's experience in the development of the language, are presented with an emphasis on the ad hoc nature of their solutions. / text

Planning for transportation within northern Canadian communities presents unique challenges, but new research tools offer opportunities for testing potentially innovative solutions that might help improve mobility within these communities. In particular, problem solving has been enriched in recent years by using the spatial modeling methods offered by Geographical Information Systems (GIS). This thesis first reviews various GIS methods before applying one method – the ‘Route Utility Theory’ – to a newly-developed set of metrics for determining the cost of alternate modes of intracommunity transportation. This set of metrics is applied to a data set that represents the trips or journeys made by non-car users in Iqaluit, the capital city of Nunavut Territory. GIS data on roads, walking trails, land contours, and public and residential neighbourhoods are analyzed. The results facilitate comparisons between road options and trail options for improving the movement of people within Iqaluit. Five bus routes were then custom designed and compared using the study’s metrics. The study found that increasing bus and trail options within Iqaluit would provide more efficient options for non-car users. It is argued that the study’s metrics can be adapted for application in other northern communities, and possibly in other isolated and rural communities in different world situations. / Graduate