Physically unclonable functions are increasingly used as security primitives for device identification and anti-counterfeiting. However, PUFs are associated with noise and bias which in turn affects its property of reliability and predictability. The noise is corrected using fuzzy extractors, but the helper data generated during the process may cause leakage in min-entropy due to the bias observed in the response. This thesis offers two optimization techniques for PUF based protocols. The first part talks about the construction of a secure enrollment solution for PUFs on a low-end resource-constrained device using a microcontroller and a secure networked architecture. The second part deals with the combined optimization of min-entropy and error-rate using symbol clustering techniques to improve the reliability of SRAM PUFs. The results indicate an increase in min-entropy without much effect on the error rate but at the expense of PUF size. / Master of Science

Recently, the resistance switching random access memory (ReRAM) in several MIM systems has been studied extensively for applications to the next generation non-volatile memory (NVM) devices and memristors since the scaling of conventional memories based on floating gate MOSFETs is getting increasingly difficult. ReRAM is being considered one of the most promising candidates for next generation non-volatile memory due to its relatively high switching speed, superior scalability, low power consumption, good retention and simple fabrication method. Cu/TaOX/Pt resistive switching device is a very good candidate due to its well performance and well characterization. However, since platinum (Pt) acting as the inert electrode is not economical efficient for industrial production, a compatible replacement of Pt is highly desirable. The device property of Co based resistive switching devices has been explored in this work. Compared with Pt devices, electric characterization of the fabricated Cu/TaOX/Co devices exhibits very similar FORM, SET and RESET voltages for Cu conductive filaments. However, for the oxygen vacancy (VO) filament the Co device has a significant smaller FORM, SET and RESET voltages of VO filament, which can be partly attributed to the work function difference between Pt and Co of 1.35 V and partly to the impaired integrity properties of Co vs Pt inert electrode. The limit of SET-RESET operations is mainly due to the geometrical shape of the Cu conductive filament is more cylindered rather than Cone-like shape as well as the high Joules heat dissipation. What’s more, ReRAM is also the most promising candidate for a flexible memory, as a variety of materials can be used both inorganics, organics and even hybrid nanocomposites. Besides inorganic ReRAM device, we also fabricated an organic ReRAM device with the structure Cu doped PANI-CSA/O-AA/Al. We have manufactured ReRAM based on Cu-doped PANI-CSA polymer electrode, O-AA as the polymer solid electrolyte and Al as the bottom electrode for the first time. This polymer device shows a significantly lower forming voltage than inorganic ReRAM devices such as Cu/TaOX/Pt. Our results also demonstrate that our organic ReRAM is a promising candidate for inexpensive candidate for inexpensive and environmentally friendly memory devices. We have demonstrated that the FORM operation of the polymer devices depends on the concentration of Cu+ ions as well as the thickness of the polymer electrode. / M.S. / Although the scaling of conventional memories such as volatile dynamic random access memory (DRAM) and non-volatile flash technology is becoming increasingly difficult, new types of non-volatile memories, such as resistive switching memories, have recently attracted the attention of both industry and academia. Resistive switching memory is considered as the next generation non-volatile memory because of its excellent scalability, high switching speed, simple structure and low power consumption. What’s more, ReRAM is also a promising candidate for a flexible memory, as a variety of materials can be used both inorganics, organics and even hybrid nanocomposites. ReRAM shows unique nanoionics based filamentary switching mechanism. Besides the nonvolatile memory applications, resistive switching devices implement the formation of a memristor, which is the fourth basic electrical component and can be used for neuromorphic computing. First, we report the device property of Co based resistive switching devices with a structure of Cu/TaOX/Co layers. The I-V characteristics of the manufactured Cu/TaOX/Co devices shows very similar FORM, SET and RESET voltages for Cu conductive filaments compared with Pt device. However, the Co device has a significant smaller FORM, SET and RESET voltages for oxygen vacancy (VO) filaments, which can be partly attributed to the work function difference between Pt and Co of 13.5 eV and partly to the impaired integrity properties of Co vs Pt inert electrode. The main reason for the limit of SET-RESET operations is that high Joules heat dissipation. With high Joules heat accumulation, the maximum switching cycles of Co devices is up to 8 times, while in the case of Pt cases, it is almost unlimited. Secondly, we fabricated an organic ReRAM device with the structure Cu-doped PANI-CSA/O-AA/Al. Cu-doped PANI-CSA polymer electrode has been introduced for the first time as the top polymer electrode of a ReRAM device. Compared to inorganic ReRAM device, this polymer device can be operated at a significantly lower forming voltage than inorganic devices such as Cu/TaOX/Pt. We have demonstrated that our organic ReRAM is a promising candidate for environmentally friendly and flexible memory devices. Our results demonstrate the FORM operation of the polymer devices depend on the concentration of Cu+ ions as well as the thickness of the polymer top layer.

The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion smart devices will be connected and online by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications. / Ph. D. / The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion “smart” devices will be connected and “online” by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications.

Memory design is a crucial component of VLSI system design from area, power and performance perspectives. To meet the increasingly challenging system specifications, architecture, circuit and device level innovations are required for existing memory technologies. Emerging memory solutions are widely explored to cater to strict budgets. This thesis presents design methodologies for custom memory design with the objective of power-performance benefits across specific applications. Taking example of STTRAM (spin transfer torque random access memory) as an emerging memory candidate, the design space is explored to find optimal energy design solution. A thorough thermal reliability study is performed to estimate detection reliability challenges and circuit solutions are proposed to ensure reliable operation. Adoption of the application-specific optimal energy solution is shown to yield considerable energy benefits in a read-heavy application called MBC (memory based computing). Circuit level customizations are studied for the volatile SRAM (static random access memory) memory, which will provide improved energy-delay product (EDP) for the same MBC application. Memory design has to be aware of upcoming challenges from not only the application nature but also from the packaging front. Taking 3D die-folding as an example, SRAM performance shift under die-folding is illustrated. Overall the thesis demonstrates how knowledge of the system and packaging can help in achieving power efficient and high performance memory design.

This thesis investigates a test method to detect the presence of Variable Retention Time (VRT) bits in manufactured DRAM. The VRT bits retention time is modeled as a 2-state random telegraph process that includes miscorrelation between test and use. The VRT defect is particularly sensitive to test and use conditions. A new test method is proposed to screen the VRT bits by simulating the use conditions during manufacturing test. Evaluation of the proposed test method required a bit-level VRT model to be parameterized as a function of temperature and voltage conditions. The complete 2-state VRT bit model combines models for the time-in-state and for the retention-time including miscorrelation. A copula is used to model the eect of miscorrelation between test and use. The proposed VRT test algorithm runtime is estimated as a function of VRT test coverage, test temperature and test voltage.

Resistive random access memory (RRAM) is a non-volatile memory technology based on resistive switching in a dielectric or semiconductor sandwiched between two different metals. Also known as memristors, these devices are potential candidates for a next-generation replacement for flash memory. In this thesis, bipolar resistive switching is reported for the first time in solution-deposited zinc-tin-oxide (ZTO). The impact of the compliance current on device operation, including the SET and RESET voltages, pre-SET, RESET and post-RESET currents, the resistance ratio between the low and high resistance states, retention, and the endurance, is investigated for an isolated Al dot/ZTO/Ir blanket device and for Al/ZTO/Pt crossbar RRAM devices. A gradual forming process is devised to improve device stability and performance. It is found that the device performance depends critically on the compliance current density that is used to limit the breakdown conduction during the SET operation. In addition, it was found that the conduction and switching mechanisms are consistent with the filament model of formation and rupture of conductive filaments. / Graduation date: 2012

The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design point for current and future VLSI systems. These systems employ large on-chip SRAM memories. Reducing memory leakage power while maintaining data integrity is a key criterion for modern day systems. Unfortunately, state of the art techniques like power-gating can only be applied to logic as these would destroy the contents of the memory if applied to a SRAM system. Fortunately, previous works have noted large temporal and spatial locality for data patterns in commerical processors as well as application specific ICs that work on images, audio and video data. This thesis presents a novel column based Energy Compression technique that saves SRAM power by selectively turning off cells based on a data pattern. This technique is applied to study the power savings in application specific inegrated circuit SRAM memories and can also be applied for commercial processors. The thesis also evaluates the effects of processing images before storage and data cluster patterns for optimizing power savings.

With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the possibility of fabrication of LBTs with a CMOS technology is established. Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same. A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.

The gradually widening speed disparity of between CPU and memory has become an overwhelming bottleneck for the development of Chip Multiprocessor (CMP) systems. In addition, increasing penalties caused by frequent on-chip memory accesses have raised critical challenges in delivering high memory access performance with tight power and latency budgets. To overcome the daunting memory wall and energy wall issues, this thesis focuses on proposing a new heterogeneous scratchpad memory architecture which is configured from SRAM, MRAM, and Z-RAM. Based on this architecture, we propose two algorithms, a dynamic programming and a genetic algorithm, to perform data allocation to different memory units, therefore reducing memory access cost in terms of power consumption and latency. Extensive and intensive experiments are performed to show the merits of the heterogeneous scratchpad architecture over the traditional pure memory system and the effectiveness of the proposed algorithms.

The main objective of this research is to provide an efficient and reliable method for using multi-level cell (MLC) phase-change memory (PCM) as a main memory. As DRAM scaling approaches the physical limit, alternative memory technologies are being explored for future computing systems. Among them, PCM is the most mature with announced commercial products for NOR flash replacement. Its fast access latency and scalability have led researchers to investigate PCM as a feasible candidate for DRAM replacement. Moreover, the multi-level potential of PCM cells can enhance the scalability by increasing the number of bits stored in a cell. However, the two major challenges for adopting MLC PCM are the limited write endurance cycle and the resistance drift issue. To alleviate the negative impact of the limited write endurance cycle, this thesis first introduces a secure wear-leveling scheme called Security Refresh. In the study, this thesis argues that a PCM design not only has to consider normal wear-out under normal application behavior, most importantly, it must take the worst-case scenario into account with the presence of malicious exploits and a compromised OS to address the durability and security issues simultaneously. Security Refresh can avoid information leak by constantly migrating their physical locations inside the PCM, obfuscating the actual data placement from users and system software. In addition to the secure wear-leveling scheme, this thesis also proposes SAFER, a hardware-efficient multi-bit stuck-at-fault error recovery scheme which can function in conjunction with existing wear-leveling techniques. The limited write endurance leads to wear-out related permanent failures, and furthermore, technology scaling increases the variation in cell lifetime resulting in early failures of many cells. SAFER exploits the key attribute that a failed cell with a stuck-at value is still readable, making it possible to continue to use the failed cell to store data; thereby reducing the hardware overhead for error recovery. Another approach that this thesis proposes to address the lower write endurance is a hybrid phase-change memory architecture that can dynamically classify, detect, and isolate frequent writes from accessing the phase-change memory. This proposed architecture employs a small SRAM-based Isolation Cache with a detection mechanism based on a multi-dimensional Bloom filter and a binary classifier. The techniques are orthogonal to and can be combined with other wear-out management schemes to obtain a synergistic result. Lastly, this thesis quantitatively studies the current art for MLC PCM in dealing with the resistance drift problem and shows that the previous techniques such as scrubbing or error correction schemes are incapable of providing sufficient level of reliability. Then, this thesis proposes tri-level-cell (3LC) PCM and demonstrates that 3LC PCM can be a viable solution to achieve the soft error rate of DRAM and the performance of single-level-cell PCM.