High aspect ratio silicon etching used for DRAM manufacturing still remains as one of the biggest challenges in semiconductor fabrication, requiring well understood and characterized process fundamentals. In this study, physical and chemical interactions during etching silicon in capacitively coupled plasma discharges were investigated in detail for different HBr/NF3 mixed chemistries for single frequency as well as dual frequency operation and medium discharge pressures inside an industrial MERIE CCP reactor typically used for DRAM fabrication. Utilization of the dual frequency concept for separate control of ion energy and ion flux, as well as the impact on discharge properties and finally on etching at relevant substrate surfaces were studied systematically. The complex nature of multi frequency rf sheaths was both analyzed experimentally by applying mass resolved ion energy analysis, and from simulation of ion energy distributions by using a Hybrid Plasma Sheath Model. Discharge composition and etch processes were investigated by employing standard mass spectrometry, Appearance Potential Mass Spectrometry, Quantum Cascade Laser Absorption Spectroscopy, rf probe measurements, gravimetry and ellipsometry. An etch model is developed to explain limitations of silicon etching in HBr/NF3 discharges to achieve highly aniostropic etching. / Siliziumätzen mit hohen Aspektverhältnissen zur Herstellung von DRAM-Speicherstrukturen stellt nach wie vor eine der größten Herausforderungen in der Halbleiterherstellung dar und erfordert ein grundlegendes Prozessverständnis. Diese Studie beinhaltet eine umfassende und detaillierte Untersuchung physikalischer und chemischer Wechselwirkungen von Siliziumätzprozessen in kapazitiv gekoppelten HBr/NF3-Gasentladungen in einem kommerziellen, typischerweise für die DRAM-Fertigung eingesetzten MERIE CCP Reaktor mit Ein- und Zweifrequenzanregung bei mittleren Entladungsdrücken. Die Anwendung eines Zweifrequenzkonzeptes zur separaten Kontrolle von Ionenenergie und Ionenstromdichte, als auch deren Einfluss auf die Entladungseigenschaften und letztendlich auf das Ätzverhalten auf relevanten Substratoberflächen wurden systematisch untersucht. Die komplexe Natur von mehrfrequenzangeregten HF-Randschichten wurde sowohl experimentell über eine Anwendung von massenaufgelöster Ionenenergieanalyse als auch rechnerisch über Simulationen von Ionenenergieverteilungsfunktionen mit Hilfe eines hybriden Plasmarandschichtmodells analysiert. Gaszusammensetzungen verschiedener Entladungen und Ätzprozesse wurden mit Hilfe von Standard-Massenspektrometrie, Schwellwert-Massenspektrometrie, Quantenkaskaden-Laserabsorptionsspektroskopie, HF-Sondenmessungen, Gravimetrie und Ellipsometrie charakterisiert. Eine neuartige Modellvorstellung zum Siliziumätzen in HBr/NF3-Entladungsgemischen liefert eine plausible Erklärung für die Limitierung der Ätzrate zum Erreichen eines hoch anisotropen Ätzverhaltens.

Indiana University-Purdue University Indianapolis (IUPUI) / This thesis presents the development, experimentation and validation of a reliable and robust system to monitor the injector pulse generated by an Engine Control Module (ECM) and send the corresponding fueling quantity to the real-time computer in a closed loop Hardware In the Loop (HIL) bench. The system can be easily calibrated for different engine platforms as well. The fueling quantity that is being injected by the injectors is a crucial variable to run closed loop HIL simulation to carry out the performance testing of engine, aftertreatment and other components of the vehicle. This research utilized Field Programmable Gate Arrays (FPGA) and Direct Memory Access (DMA) transfer capability offered by National Instruments (NI) Compact Reconfigurable Input-Output (cRIO) to achieve high speed data acquisition and delivery. The research was conducted in three stages. The first stage was to develop the HIL bench for the research. The second stage was to determine the performance of the system with different threshold methods and different sampling speeds necessary to satisfy the required accuracy of the fueling quantity being monitored. The third stage was to study the error and its variability involved in the injected fueling quantity from pulse to pulse, from injector to injector, between real injector stators and cheaper inductor load cells emulating the injectors, over different operating conditions with full factorial design of experimentation and mixed model Analysis Of Variance (ANOVA). Different thresholds were experimented to find out the best thresholds, the Start of Injection (SOI) threshold and the End of Injection (EOI) threshold that captured the injector “ontime” with best reliability and accuracy. Experimentation has been carried out at various data acquisition rates to find out the optimum speed of data sampling rate, trading off the accuracy of fueling quantity. The experimentation found out the expected error with a system with cheaper solution as well, so that, if a test application is not sensitive to error in fueling quantity, a cheaper solution with lower sampling rate and inductors as load cells can be used. The statistical analysis was carried out at highest available sampling rate on both injectors and inductors with the best threshold method found in previous studies. The result clearly shows the factors that affect the error and the variability in the standard deviations in error; it also shows the relation with the fixed and random factors. The real-time application developed for the HIL bench is capable of monitoring the injector waveform, using any fueling ontime table corresponding to the platform being tested, and delivering the fueling quantity in real-time. The test bench made for this research is also capable of studying injectors of different types with the automated test sequence, without occupying the resource of fully capable closed loop test benches for testing the ECM unctionality.

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μ W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μ W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications.

Thin-film transistors (TFTs) are primarily used as a switching element in liquid crystal displays. Currently, amorphous silicon is the dominant TFT technology for displays, but higher performance TFTs will become necessary to enable ultra-definition resolution high-frequency large-area displays. Amorphous zinc tin oxide (ZTO) TFTs were fabricated by RF magnetron sputter deposition. In this study, the effect of both deposition and post annealing conditions have been evaluated in regards to film structure, composition, surface contamination, and device performance. Both the variation of oxygen partial pressure during deposition and the temperature of the post-deposition annealing were found to have a significant impact on TFT properties. X-ray diffraction data indicated that the ZTO films remain amorphous even after annealing to 600° C. Rutherford backscattering spectrometry indicated that the Zn:Sn ratio of the films was ~1.7:1 which is slightly tin rich compared to the sputter target composition. X-ray photoelectron spectroscopy data indicated that the films had significant surface contamination and that the Zn:Sn ratios changed depending on sample annealing conditions. Electrical characterization of ZTO films using TFT test structures indicated that mobilities as high as 17 cm² V⁻¹ s⁻¹ could be obtained for depletion mode devices. It was determined that the electrical properties of ZTO films can be precisely controlled by varying the deposition conditions and annealing temperature. It was found that the ZTO electrical properties could be controlled where insulating, semiconducting and conducting films could be prepared. This precise control of electrical properties allowed us to incorporate sputter deposited ZTO films into resistive random access memory (RRAM) devices. RRAM are two terminal nonvolatile data memory devices that are very promising for the replacement of silicon-based Flash. These devices exhibited resistive switching between high-resistance states to low-resistance states and low-resistance states to high-resistance states depending on polarity of applied voltages and current compliance settings. The device switching was fundamentally related to the defect states and material properties of metal and insulator layers, and their interfaces in the metalinsulator-metal (MIM) structure. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from Jan. 6, 2012 - Jan. 6, 2013

Cette étude porte sur des oxydes TiO2, SrTiO3 et SrZrO3 déficients en oxygène ou dopés par des ions de métaux de transition. Nous avons préparé des échantillons sous forme de polycristaux, de monocristaux et de films minces. Leurs propriétés structurelles, physiques et électroniques ont été mesurées à l’aide de techniques sensibles aux volumes (diffraction des rayons X, magnétométrie SQUID, résonance paramagnétique électronique) ou sensibles aux surfaces (spectroscopie de photoémission, spectroscopie d’absorption X). Les mesures de RPE et au SQUID permettent non seulement d’obtenir leurs propriétés magnétiques mais également la valence des ions Cr dopant. Nous avons ainsi pu établir les paramètres clés qui contrôlent la valence des ions chrome lors de la synthèse. Des phases secondaires telles que SrCrO4 peuvent se former quand les échantillons sont synthétisés dans des atmosphères riches en oxygène. Les propriétés de films SrZrO3 dopés au chrome sont également discutées. Leurs conditions de préparation influencent non seulement le comportement des ions chrome mais également celui de la commutation de résistivité. Ce dernier semble dépendre de la chimie de surface des films. L’accumulation d’ions Cr3+ au voisinage de la surface fournit une interface propre exempte d’oxydes non stœchiométriques. Cette terminaison nette de l’interface a pour résultat de bonnes performances de la commutation de résistivité. / In this study, the oxygen-deficient TiO2, SrTiO3 systems and transition metal ion (Cr or V) doped TiO2, SrTiO3 and SrZrO3 systems have been investigated. We prepared samples as polycrystals, single crystals and thin films for various desires. Their structural, physical and electronic properties were measured by bulk-sensitive techniques (X-Ray Diffraction, SQUID and Electro Paramagnetic Resonance) or surface-sensitive techniques (Photoemission spectroscopy and X-ray absorption spectroscopy). The measurement of SQUID and EPR showed not only their magnetic properties but also the valence state of Cr dopant. We verified the valence state of Cr ions in oxides and found the key parameters of sample synthesis which control the valence state of Cr ions. Segregated phases such as SrCrO4 were formed when the samples were synthesized under O2 rich environment. The surface properties of Cr doped SrZrO3 films are also discussed. We found the synthesis conditions which influence on not only the behavior of Cr ions but also the resistive-switching behaviors. Various resistive-switching behaviors seem to depend on the surface chemistry of films. We found that the accumulation of Cr3+ on film surface provides a clean interface without any non-stoichiometric oxides and that this sharp interface termination results in a good performance of resistive-switching.

Silicon based 3D fin structure is believed to be the potential future of current semiconductor technology. However, there are significant challenges still exist in realizing a manufacturable fin based process. In this work, we have studied the effects of hydrogen anneal on the structural and electrical characteristics of silicon fin based devices: tri-gate, finFET to name a few. H₂ anneal is shown to play a major role in structural integrity and manufacturability of 3D fin structure which is the most critical feature for these types of devices. Both the temperature and the pressure of H₂ anneal can result in significant alteration of fin height and shape as well as electrical characteristics. Optimum H₂ anneal is required in order to improve carrier mobility and device reliability as shown in this work. A new hard-mask based process was developed to retain H₂ anneal related benefit while eliminating detrimental effects such as reduction of device drive current due to fin height reduction. We have also demonstrated a novel 1T-1C pseudo Static Random Access Memory (1T-1C pseudo SRAM) memory cell using low cost conventional tri-gate process by utilizing selective H₂ anneal and other clever process techniques. TCAD-based simulation was also provided to show its competitive advantage over other types of static and dynamic memories in 45nm and beyond technologies. A high gain bipolar based on silicon fin process flow was proposed for the first time that can be used in BiCMOS technology suitable for low cost mixed signal and RF products. TCAD-based simulation results proved the concept with gain as high 100 for a NPN device using single additional mask. Overall, this work has shown that several novel process techniques and selective use of optimum H₂ anneal can lead to various high performance and low cost devices and memory cells those are much better than the devices using current conventional 3D fin based process techniques. / text

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis. / Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal.

A 2T2C ferroelectric memory cell consisting of a select transistor, a read transistor and two ferroelectric capacitors that can be operated either in FeRAM mode or in memristive ferroelectric tunnel junction mode is proposed. The two memory devices can be programmed individually. By performing a combined readout operation, the two stored bits of the memory cells can be combined to perform in-memory logic operation. Moreover, additional input logic signals that are applied as external readout voltage pulses can be used to perform logic operation together with the stored logic states of the ferroelectric capacitors. Electrical characterization results of the logic-in-memory (LiM) functionality is presented.

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μ W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μ W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications.

Discusses the structure and topology of dynamic memory chips, the impact of the environment on the information storage process, ways to control and correct errors that occur during storage of data; in Matlab / Simulink, a model is constructed of dynamic memory cells in conditions close to the natural background radiation; a comparative analysis of noise immunity in the absence of storage and use of the Hamming code. / Рассматриваются структура и топология микросхем динамической памяти, влияние внешней среды на процесс хранения информации, способы контроля и исправления ошибок, возникающие при хранении данных; в среде Matlab/Simulink построена модель ячейки динамической памяти в условиях приближенных к естественному радиационному фону; проведен сравнительный анализ помехоустойчивости хранения данных при отсутствии и использовании кода Хемминга.