A mixed-signal reconfigurable platform gives the designer the choice of implementing systems using the benefits of both analog and digital circuits. The subject of this research is the implementation and application of mixed-signal reconfigurable systems utilizing floating-gate transistors and field programmable analog/digital arrays. Basic analog circuits using floating-gate CMOS devices have been developed for this research. Floating-gate based analog circuits reduce the effects of inherent property mismatch present in analog circuits. Various circuit blocks including current mirrors, gilbert multipliers, and $G_m-C$ filters were designed and experimentally demonstrated to show reduced mismatch effects. Such floating-gate transistors and circuits are the basis for the reconfigurable systems developed in this research. To enable high-performance reconfigurable systems, sub-micron and sub-$100 nm$ CMOS process nodes were used in this research. Scaling of Floating-gate devices is a key issue at small nodes. Test structures were created to verify the programming capability for floating-gate devices at various process nodes. Experimental results show scalability of floating-gate devices along with effective charge programming ability. A floating-gate based reconfigurable mixed-signal platform using Field-Programmable Array of Analog-Digital Devices (FPAADD) has been created and experimentally verified. Further FPAADD systems augmented with a CPU based digital back-end were developed to enable greater applications for such reconfigurable systems. Experimental functionality and circuits/systems created using FPAADD based systems were demonstrated for this research work.

Yes / Cooperative Systems of Systems (CSoS) including Autonomous systems (AS), such as autonomous cars and related smart traffic infrastructures form a new technological frontier for their enormous economic and societal potentials in various domains. CSoS are often safety-critical systems, therefore, they are expected to have a high level of dependability. Due to the open and adaptive nature of the CSoS, the conventional methods used to provide safety assurance for traditional systems cannot be applied directly to these systems. Potential configurations and scenarios during the evolving operation are infinite and cannot be exhaustively analysed to provide guarantees a priori. This paper presents a novel framework for dynamic safety assurance of CSoS, which integrates design time models and runtime techniques to provide continuous assurance for a CSoS and its systems during operation. / Dependability Engineering Innovation for Cyber Physical Systems (DEIS) H2020 Project under Grant 732242.

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No / Software radio and reconfigurable systems represent reconfigurable functionalities of the radio interface. Considering turbo decoding function in battery-powered devices like 3GPP mobile terminals, it would be desirable to choose the optimum decoding algorithm: SOVA in terms of latency, and log-MAP in terms of performance. In this paper it is shown that the two algorithms share common operations, making feasible a reconfigurable SOVA/log-MAP turbo decoder with increased efficiency. Moreover, an improvement in the performance of the reconfigurable architecture is also possible at minimum cost, by scaling the extrinsic information with a common factor. The implementation of the improved reconfigurable decoder within the 3GPP standard is also discussed, considering different scenarios. In each scenario various frame lengths are evaluated, while the four possible service classes are applied. In the case of AWGN channels, the optimum algorithm is proposed according to the desired quality of service of each class, which is determined from latency and performance constraints. Our analysis shows the potential utility of the reconfigurable decoder, since there is an optimum algorithm for most scenarios.

No / Self-adaptive systems are evolving systems that can adjust their behaviour to accommodate dynamic requirements or to better serve the goal. These systems can vary in their architecture, operation, or adaptive strategies based on the application. Moreover, the evaluation can happen in different ways depending on system architecture and its requirements. Self-adaptive systems can be prone to situations like adaptation faults, inconsistencies in context or low performance on tasks due to their dynamism and complexity. That is why it is important to have reliability assurance of the system to monitor such situations which can compromise the system functionality. In this paper, we provide a brief background on different types of self-adaptive systems and various ways a system can evolve. We discuss the different mechanisms that have been applied in the last two decades for reliability evaluation of such systems and identify challenges and limitations as research opportunities related to the self-adaptive system’s reliability evaluation. / This research was undertaken as a part of the “Model-based Reliability Evaluation for Autonomous Systems with Evolving Architectures” project funded by the University of Bradford under the SURE Grant scheme.

Due to their programmable nature, Field Programmable Gate Arrays (FPGAs) offer a good test environment for reconfigurable systems. FPGAs can be reconfigured during the operation with changing demands. This feature, known as Runtime Reconfiguration (RTR), can be used to speed-up computations and reduce system cost. Moreover, it can be used in a wide range of applications such as adaptable hardware, fault tolerant architectures. This thesis is mostly concentrated on the runtime reconfigurable architectures. Critical properties of runtime reconfigurable architectures are examined. As a case study, a Triple Modular Redundant (TMR) system has been implemented on a runtime reconfigurable FPGA. The runtime reconfigurable structure increases the system reliability against faults. Especially, the weakness of SRAM based FPGAs against Single Event Upsets (SEUs) is eliminated by the designed system. Besides, the system can replace faulty elements with non-faulty elements during the operation. These features of the developed architecture provide extra safety to the system also prolong the life of the FPGA device without interrupting the whole system.

Field-programmable gate arrays (FPGAs) have the potential to address scaling challenges in CMOS technology because of their regular structures and the flexibility they possess by being re-configurable after fabrication. One of the potential approaches in attacking scaling challenges, such as negative-bias temperature instability (NBTI) and process variation (PV), is by using placement techniques that are aware of these problems. Such techniques aim at placing a circuit in an FPGA such that the critical path delay is improved compared to the expected worst case. This can be achieved by placing NBTI-critical blocks of a circuit in areas with fast transistors in an FPGA chip. In this thesis, we present a detailed research effort that addresses the joint effect of NBTI and PV in FPGAs. We follow an experimental methodology in that we use actual PV data that we measure from 15 FPGA chips. The measured data is used to study the joint effect of NBTI and PV on the timing performance of circuits that are placed and routed in FPGAs. Enhancements are made to a well-known FPGA placement algorithm, T-VPlace, in order to make the placement process aware of the joint effect of NBTI and PV. Results are given for the placement and routing of Microelectronics Center of North Carolina (MCNC) benchmark circuits to show the effectiveness of the proposed techniques in addressing scaling challenges in FPGAs. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2009-09-24 17:23:29.626

abstract: The following document describes the hardware implementation and analysis of Temporal Interference Mitigation using High-Level Synthesis. As the problem of spectral congestion becomes more chronic and widespread, Electromagnetic radio frequency (RF) based systems are posing as viable solution to this problem. Among the existing RF methods Cooperation based systems have been a solution to a host of congestion problems. One of the most important elements of RF receiver is the spatially adaptive part of the receiver. Temporal Mitigation is vital technique employed at the receiver for signal recovery and future propagation along the radar chain. The computationally intensive parts of temporal mitigation are identified and hardware accelerated. The hardware implementation is based on sequential approach with optimizations applied on the individual components for better performance. An extensive analysis using a range of fixed point data types is performed to find the optimal data type necessary. Finally a hybrid combination of data types for different components of temporal mitigation is proposed based on results from the above analysis. / Dissertation/Thesis / Masters Thesis Computer Engineering 2020

Yes / The advances in the Internet of Things (IoT) has substantially contributed to the automation of modern societies by making physical things around us more interconnected and remotely controllable over the internet. This technological progress has inevitably created an intelligent society where various mechatronic systems are becoming increasingly efficient, innovative, and convenient. Undoubtedly, the IoT paradigm will continue to impact human life by providing efficient control of the environment with minimum human intervention. However, despite the ubiquity of IoT devices in modern society, the dependability of IoT applications remains a crucial challenge. Accordingly, this paper systematically reviews the current status and challenges of IoT dependability frameworks. Based on the review, existing IoT dependability frameworks are mainly based on informal reliability models. These informal reliability models are unable to effectively evaluate the unified treatment safety faults and cyber-security threats of IoT systems. Additionally, the existing frameworks are also unable to deal with the conflicting interaction between co-located IoT devices and the dynamic features of self-adaptive, reconfigurable, and other autonomous IoT systems. To this end, this paper suggested the design of a novel model-based dependability framework for quantifying safety faults and cyber-security threats as well as interdependencies between safety and cyber-security in IoT ecosystems. Additionally, robust approaches dealing with conflicting interactions between co-located IoT systems and the dynamic behaviours of IoT systems in reconfigurable and other autonomous systems are required.

Sistemas Dinamicamente Reconfiguráveis (SDRs) tem sido aceitos como alternativa importante para diminuir os custos de circuitos digitais. Porém, eles adicionam novas dimensões no projeto de Sistemas sobre Silício (System-On-Chip, SoC). Apesar de novas metodologias terem sido propostas por fabricantes de FPGA para lidar com a complexidade deste tipo de circuitos, as soluções ainda são muito específicas. Considerando-se que o uso de recursos de comunicação robustos em SoCs complexos atuais é generalizado, os meios de comunicação estruturados, como rede Intrachips (Network-On-Chip, NoCs), foram incluídas em sistemas dinamicamente reconfiguráveis, gerando-se arquiteturas de SDRs baseadas em NoCs, ou de SDR-NoCs. Arquiteturas de SDR-NoCs podem ser simples ou complexas. As arquiteturas de SDR-NoCs simples são aquelas com topogias regulares e diretas e Módulos Processantes (MPs) homogêneos. As arquiteturas de SDR-NoCs complexas são aquelas com topologias irregulares e indiretas com MPs heterogêneos. O mapeamento é a fase no fluxo de projeto do SoC que visa encontrar a melhor localização das unidades de processamento da aplicação junto à topologia da NoC, de tal forma que as métricas de interesse podem ser otimizadas. O problema do posicionamento lida com a alocação otimizada de recursos (cores) dentro do dispositivo reconfigurável. No mapeamento de SDR-NoCs, a capacidade de reconfiguração no tempo acrescenta uma nova dimensão ao problema de mapeamento, uma vez que diferentes cores são atribuídos ao mesmo roteador, mas estão presentes no dispositivo em momentos distintos. Para arquiteturas de SDR-NoCs complexas, o problema de mapeamento está fortemente associado ao problema do posicionamento e convém tratá-los em conjunto. Até o presente momento, o problema de mapeamento e posicionamento para SDR-NoCs não tem sido tratados adequadamente. Neste trabalho são apresentadas soluções para o mapeamento e/ou posicionamento de MPs para arquiteturas SDR-NoCs tanto simples quanto complexas. Primeiramente, uma estratégia de mapeamento é proposta para arquiteturas simples, de uma forma que torna possível a utilização de estratégias de mapeamento clássicas anteriores (sem reconfiguração) para SDRs. Os resultados mostram a redução de até 38%, no atraso médio da NoC e de até 41% de economia de energia comparando a melhor solução com a média de soluções aleatórias. Em uma segunda fase, o problema de mapeamento e posicionamento são tratados em conjunto para arquiteturas SDR-NoCs complexas: uma formalização do problema é proposta e um algoritmo exato, semi-exaustivo, é implementado e utilizado para a a sua análise. Devido à alta complexidade do problema, um segundo algoritmo genético (Genetic Algorithm, GA) foi implementado para que casos maiores possam ser resolvidos. Vários tipos de crossover e metodologias de GAs são comparadas para se obter a melhor solução. Os resultados mostram que a melhor solução GA obteve, em média, custos de comunicação com 4% de penalidade quando comparada com a melhor solução, sendo que o algoritmo apresenta bons tempos de execução. / Dynamic Reconfigurable Systems (DRSs) have been accepted as an important alternative for lowering costs of digital circuits. However, they add new dimensions to the system-on-chip (SoC) design space. Although new methodologies have been proposed by Field Programmable Gate Arrays (FPGAs) manufacturers to deal with the increased design complexity in this class of circuits, solutions to the algorithmic and block level design are still very ad-hoc. Considering the generalized use of robust communication resources in current complex SoCs, structured communication means, as network-on-chips (NoCs), have been included in dynamic reconfigurable systems generating DRSs based on NoCs, or DRS-NoCs, under different architectures. DRS-NoC architectures can be simple or complex. Simple DRS-NoCs architectures refer to regular and direct NoC topologies, with homogeneous Processing Modules (PMs). Complex DRS-NoCs architectures refer to irregular and undirected NoC topologies, with heterogeneous MPs. Mapping is the step in the SoC design flow which aims to find the best topological location for the application processing units onto the NoC topology, such that the metrics of interest can be greatly optimized. The placement problem deals with the optimized allocation of resources (cores) inside the reconfigurable device. In DRS-NoCs mapping, the on-going reconfiguration capability adds a new dimension to the mapping problem, since different cores are assigned to the same router, but being present in the in the logic fabric in separate moments. Furthermore, in complex DRS-NoC architectures the mapping problem is strongly associated with the placement one, and they should be dealt concurrently. To the date, the mapping and placement problems have not been properly addressed for those kind of architectures. In this work solutions are presented for hardware core placement and/or mapping for both simple and complex DRS-NoC architectures. Firstly, a mapping strategy is proposed for simple architectures, in a way that makes it possible to use previous classic mapping strategies (without reconfiguration) for DRSs. Results show reductions up to 38% on the average NoC delay and up to 41% of energy saving when comparing the best solution with average random solutions. In the second phase, the mapping and placement problems are dealt concurrently for DRS-NoC complex architectures: the problem formalization is proposed and for its analysis, an exact, and semi-exaustive, algorithm is implemented and applied. Due to the high complexity associated to the problem, an Genetic Algorithm (GA) was implemented to deal with larger cases. Several GAs crossovers and methodologies are compared for obtaining the best solution. Results show that best GA solution obtained, in average, communication costs with 4% of penalty when compared with best solution. In addition, the algorithm presents low execution times.