In the past few decades, Si-based CMOS technology is approaching to its physical quantum limit by scaling down the gate length and gate oxide thickness to achieve higher drive current for low power and high speed application. High k/III-V stack provides an alternative solution because III-V based metal-oxide-semiconductor (MOS) devices have higher drive current due to the higher electron mobility than silicon. Also high k oxides lower the gate leakage current significantly due to larger thickness under the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. The main obstacle for high k/III-V based MOSFETs is the lack of high quality, thermodynamically stable insulators that passivate the interface, which is also the main driving force in the research area of high k/III-V stack. One of the main focuses of this dissertation is developing a fabrication process flow to lower the interface trap density to enhance the performance of MOSFETs with high k oxides on III-V substrates. Also, an emerging memory device with SiO[subscript x] is also developed. This device can be electrically switched between a high-resistance state (HRS, or OFF-state) and a low-resistance state (LRS, or ON-state). Also it shows high potential for next generation nonvolatile memories due to its small cell area, fast write/erase time, low write voltage, good endurance and scalability. The other main focuses of this dissertation is studying the electroforming, set/reset voltages and passivation issue in this resistive random access memory (RRAM or ReRAM). The first part of this dissertation is about lowering the interface trap density of high k/III-V stack by using a thin layer of Al₂O₃ or LaAlO₃. ALD Al₂O₃/HfO₂ bi-layer gate oxide with different Al₂O₃ thickness (0, 5, 10Å) was deposited. Also ALD LaAlO₃/HfO₂ bi-layer gate oxide with different LaAlO₃ thickness (0, 5, 10, 20, 30, 42Å) was deposited. The total EOT of the bi-layer was maintained at ~1.8nm. Also single La[subscript x]Al[subscript 1-X]O (X =0.25, 0.33, 0.5, 0.66, 0.75) gate dielectric with different La doping level was deposited (EOT=2.5±0.4nm). Device characteristics are compared by using different thickness of interfacial layer. The second part of this dissertation is about F incorporation into high k oxide by using SF₆ plasma. The effect of SF₆ plasma treatment of HfO₂ on III-V substrates is demonstrated. Also effect of different plasma power and different treatment time of SF₆ plasma is studied to optimize plasma conditions. High k bilayer (Al₂O₃/HfO₂) is also used to further improve the device performance by better interface passivation with Al₂O₃. HfO₂ gate oxide dielectric is also engineered using SF₆ plasma treatment to incorporate more F. The third part is a study of III-V tunneling FET using In[subscript 0.7]Ga[subscript 0.3]As p-n junction. The device performance with different n doping concentration is compared. Higher n doping concentration will increase the drive current by reducing the tunneling width while too higher n doping concentration results in tunneling in the middle of p-n junction and significantly increase the subthreshold swing. The forth part is the electroforming, set/reset and passivation study of ReRAM device with SiO[subscript x]. Different methods to reduce the electroforming voltage are developed. Set/reset process is also studied and a possible model is proposed to explain the set/ reset process. A new device structure without sidewall edge is studied for passivation and application in air. The final part is the summary of Ph.D work and also suggestions for future work are discussed. / text

Current CMOS-based technologies are facing design challenges related to the continuous scaling down of the minimum feature size, according to Moore’s law. Moreover, conventional computing architecture is no longer an effective way of fulfilling modern applications demands, such as big data analysis, pattern recognition, and vector processing. Therefore, there is an exigent need to shift to new technologies, at both the architecture and the device levels. Recently, memristor devices and structures attracted attention for being promising candidates for this job. Memristor device adds a new dimension for designing novel circuits and systems. In addition, high-density memristor-based crossbar is widely considered to be the essential element for future memory and bio-inspired computing systems. However, numerous challenges need to be addressed before the memristor genuinely replaces current memory and computing technologies, which is the motivation behind this research effort. In order to address the technology challenges, we begin by fabricating and modeling the memristor device. The devices fabricated at our local clean room enriched our understanding of the memristive phenomenon and enabled the experimental testing for our memristor-based circuits. Moreover, our proposed mathematical modeling for memristor behavior is an essential element for the theoretical circuit design stage. Designing and addressing the challenges of memristor systems with practical complexity, however, requires an extra step, which takes the form of a reliable and modular simulation platform. We, therefore, built a new simulation platform for the resistive crossbar, which can simulate realistic size arrays filled with real memory data. In addition, this simulation platform includes various crossbar nonidealities in order to obtain accurate simulation results. Consequently, we were able to address the significant challenges facing the high density memristor crossbar, as the building block for resistive-based memory systems and neural computing. For gateless arrays, we present multiport array structure and readout technique, which for the first time introduces a closed-form solution for the challenging crossbar sneak-paths problem. Moreover, a new adaptive threshold readout methodology is proposed, which employs the memory hierarchy locality property in order to improve the access time to the memristor crossbar. Another fast readout technique based on binary counters is presented for locality-less crossbar systems. On the other hand, for gated arrays, we present new readout technique and circuitry that combines the advantages of the gated and gateless memristor arrays, namely the high-density and low-power consumption. In general, the presented structures and readout methodologies empower much faster and power efficient access to the high-density memristive crossbar, compared to other works presented in the literature. Finally, at the circuit level, we propose novel reactance-less oscillators based on memristor devices, which find promising applications in embedded systems and bio-inspired computing. Altogether, we believe that our contributions to the emerging technology help to push it to the next level, shortening the path towards better futuristic computing systems.

Les mémoires résistives à base d’oxyde OxRAM sont une technologie de mémoire non-volatile dite émergente, au même titre que les mémoires à changement de phase (PCRAM) ou les mémoires magnétorésistives (MRAM). A l’origine les OxRAM étaient très étudiées pour concurrencer les mémoires Flash, dont le fonctionnement est basé sur le stockage de charges dans une grille flottante. Cependant, avec l’avènement des technologies 3D-NAND, il semble très difficile pour les OxRAM d’atteindre les mêmes capacités de stockage que les flashs. Cependant, leur impressionnante vitesse de fonctionnement, bien supérieure à celle des NAND, et leur coût bien inférieur à celui des DRAM, leur permet de se situer à la frontière entre ces deux technologies, dans une catégorie qualifiée de « Storage Class Memory ». De plus, il s’agit d’une technologie dont l’intégration en Back-End-Of-Line, juste au-dessus des circuits CMOS, est très facile, ce qui la rend très attrayante. En revanche, les OxRAM sont connues pour présenter une forte variabilité, et cela représente le principal obstacle à leur démocratisation.Au cours de cette thèse, nous avons cherché à étudier en profondeur la dynamique de commutation résistive de mémoires OxRAM à base d’oxyde d’hafnium, avec une volonté de se concentrer sur des temps très courts, puisqu’ils représentent l’un des atouts majeurs de cette technologie. Pour cela, ces travaux de thèse se concentrent tout d’abord sur un aspect expérimental, de caractérisation électrique. Nous avons ainsi pu observer, avec un suivi dynamique, la commutation résistive des mémoires, sur des temps de l’ordre de la dizaine de nanoseconde, pour les opérations d’écriture et d’effacement, via la mise au point d’un banc de test entièrement dédié à cette tâche. Ensuite, nous avons analysé les impacts que la réduction du temps de pulse, ainsi que l’abaissement des courants et tensions mis en jeu, peuvent avoir sur la fiabilité des OxRAM, avec des mesures de variabilité. La seconde partie de ce travail de thèse est un travail de modélisation, avec la mise au point d’un modèle physique semi-analytique, dans le but de comprendre les mécanismes de commutation résistives. Après avoir comparé les résultats obtenus par notre modèle aux résultats expérimentaux précédents, nous avons cherché à appliquer notre modèle à des mesures de statistiques. Nous avons ainsi réalisé des tests électriques sur des matrices OxRAM, que nous avons tenté de reproduire avec le modèle. Enfin, nous avons étudié plus en profondeur le bruit à basse fréquence dans les OxRAM, qui constitue l’un des facteurs majeurs de dégradation de la fiabilité des OxRAM, tout en cherchant des pistes pour le diminuer. / Oxyde-based resistive memories OxRAM are a technology of emergent non-volatile memory, as phase-change memories (PCRAM) or magnetoresistive memories (MRAM). In the beginning OxRAM were very studied in order to compete with Flash memories, whose mechanism relies on the storage of electrical charges in a flotting gate. However, with the arising of 3D-NAND technology, it seems very difficult for OxRAM to reach the same storage capacities as Flash memories. But their impressive operating speed, far higher than NAND’s, and their cost far lower than DRAM’s, allow them to operate at the border of these two technologies, in a category called « Storage Class Memory ». Furthermore, the integration of OxRAM in the Back-End-Of-Line, just above CMOS circuits, makes this technology very attractive. On the other hand, OxRAM are known to have a very strong variability, which represents the main obstacle to their expansion.In this thesis, the dynamics of the resistive switching of hafnium oxyde based OxRAM has been investigated, with a desire to focus on very short times, as they are one of the main assets of this technology. To do so, our work first focuses on an experimental aspect, with electrical characterization. We were able to watch, with a dynamical monitoring, the resistive switching of the memories, at the scale of the dozen of nanoseconds, for writing and erasing operations, thanks to an entirely dedicated set-up. Then, the impacts that the time reduction, and the lowering of the voltage and current, can have on the reliability of OxRAM, were analysed, with variability measurements. The second part of this work concerns modelisation, with the elaboration of a physics-based, semi-analytical model, in order to understand the switching mechanisms. After the comparison of the results obtained by our model with the experimental ones, our model has been applied to statistical measurements. Electrical tests on OxRAM arrays have been performed, and fitted by the model. Finally, the low frequency noise (RTN) in OxRAM has been studied, as it stands as one of the main factors of degradation of OxRAM reliability. Ideas to improve the robustness of OxRAM against RTN are suggested.

In recent years, due to the rapid development of electronic products, non-volatile memory has become more and more important. However, flash memory has faced some physical limits bottleneck with size scaling-down. In order to overcome this problem, alternative memory technologies have been extensively investigated, including ferroelectric random access memory (FeRAM), magneto resistive RAM (MRAM), phase-change RAM (PRAM), and resistive RAM (RRAM). All of this potential next generation non-volatile memory, the resistive random access memory has most advantages such as simple structure, lower consumption of energy, lower operating voltage, high operating speed, high storage time and non-destructive access, which make it be the most potential candidate of the next generation non-volatile memory. Many studies have proposed to explain the resistance switching phenomenon, which is due to the metallic filament or the oxygen vacancies. Therefore, in order to investigate the influence of resistance switching characteristic by metal or oxygen, we choose the non-metal contained boron oxy-nitride film as the insulator layer and successfully make the resistance has the switchable characteristic of this device. Furthermore, we improved the iv stability by using the Gadolinium-doped method in the boron oxy-nitride based film. In addition, we observed the negative current differential phenomenon during the set process, which can further controlled by lower operating voltage to achieve the interfacial resistance switching. We think that is due to the formation of nitrogen titanium oxide at the interface between insulator layer and titanium nitride electrode, which caused the Schottky barrier formation and reduced the current flow. In addition, current conduction fitting can also confirm this hypothesis. Besides, titanium nitride easily bond with oxygen ions; moreover, the oxygen ions can be easily disturbed at higher temperature ambient. We believed there may easily form the nitrogen titanium oxide layer in higher temperature environment; which also improve by a series of varied temperature experiments. However, this nitrogen titanium oxide layer formed naturally very easily, resulting in an inevitable problem of data retention time, which wish to be resolved in the future.

Les mémoires résistives ReRAM (ou memristors) sont destinées à remplacer les mémoires non volatiles Flash. Les ReRAM utilisent le changement de résistance d’une structure MIM (Métal-Isolant-Métal) soumise à un stress en tension. Jusqu’à présent, l’attention était focalisée sur les mécanismes qui régissent la commutation de résistance dans les dispositifs ReRAM. Moins d’attention a été accordée à la variation de capacitance, c'est-à-dire à la variation de capacité des structures MIM lorsque ces dernières sont soumises à un stress en tension. C’est sur ce dernier point que notre travail porte. Nous étudions la variation d’impédance (conductance et capacitance dans le domaine RF) dans des structures MIM à base de HfO2. Au-delà d’une tension seuil (Set) une diminution de la capacitance est observée, conjointement à une augmentation de conductance. Des cycles mémoires capacité-tension (C-V) et conductance-tension (G-V) sont obtenus de manière reproductible. Des caractérisations en fréquence (C-f et G-f), sous différentes polarisations continues, sont effectuées pour mieux comprendre les mécanismes de commutation de l’impédance. La diminution de capacitance dans l’état conducteur (ON) est attribuée au caractère inductif des filaments conducteurs formés pendant l’étape de Set. Les mécanismes de transport conduisant à l’apparition de ce caractère inductif sont discutés. Nous montrons également l’influence du procédé de dépôt (ALD) de HfO2 sur les caractéristiques C-V et G-V, ainsi que les modifications apportées par l’emploi d’une structure bicouche. Ce travail ouvre la voie à la réalisation de dispositifs à mémoire de capacitance (mem-capacitors), et plus généralement de composants à mémoire d’impédance (ZRAM). Le potentiel de ces dispositifs pour réaliser un filtre reconfigurable (programmable en tension) est démontré d’une manière pratique. / Resistive random access memories (ReRAM) hold great potential for replacing Flash memories. A ReRAM memory (or MEMRISTOR) uses a resistive switching phenomenon found in Metal-Insulator-Metal (MIM) structures under a voltage stress. Most researches were focused on the mechanisms governing the resistance switching in ReRAM devices and less attention has been paid to capacitance variation of MIM structures under a voltage stress. Our work is focused on that latter phenomenon. We study impedance variation (conductance and capacitance in the RF domain) in HfO2-based MIM structures. Above a threshold voltage (Set), concurrently to conductance increase, a decrease in the capacitance value is observed. Reproducible capacitance-voltage (C-V) and conductance-voltage (G-V) memory cycles are obtained. Frequency dependent characterizations (C-f and G-f), under different DC bias voltages, are performed with the aim of understanding the mechanisms of impedance switching. The capacitance decrease observed in the conducting (ON) state is attributed to the inductance of the filament created during the Set stage. Transport phenomena responsible for the filament inductive behavior are discussed. Impact of HfO2 deposition process (ALD), as well as the use of bi-layer structures, on C-V and G-V characteristics are shown. This work paves the way for the realization of new capacitance memory devices (mem-capacitors) and most generally for impedance memories (ZRAM). Potential of these devices to design reconfigurable filters (controlled by voltage bias) is demonstrated in a practical way.

abstract: Chalcogenide glass (ChG) materials have gained wide attention because of their applications in conductive bridge random access memory (CBRAM), phase change memories (PC-RAM), optical rewritable disks (CD-RW and DVD-RW), microelectromechanical systems (MEMS), microfluidics, and optical communications. One of the significant properties of ChG materials is the change in the resistivity of the material when a metal such as Ag or Cu is added to it by diffusion. This study demonstrates the potential radiation-sensing capabilities of two metal/chalcogenide glass device configurations. Lateral and vertical device configurations sense the radiation-induced migration of Ag+ ions in germanium selenide glasses via changes in electrical resistance between electrodes on the ChG. Before irradiation, these devices exhibit a high-resistance `OFF-state' (in the order of 10E12) but following irradiation, with either 60-Co gamma-rays or UV light, their resistance drops to a low-resistance `ON-state' (around 10E3). Lateral devices have exhibited cyclical recovery with room temperature annealing of the Ag doped ChG, which suggests potential uses in reusable radiation sensor applications. The feasibility of producing inexpensive flexible radiation sensors has been demonstrated by studying the effects of mechanical strain and temperature stress on sensors formed on flexible polymer substrate. The mechanisms of radiation-induced Ag/Ag+ transport and reactions in ChG have been modeled using a finite element device simulator, ATLAS. The essential reactions captured by the simulator are radiation-induced carrier generation, combined with reduction/oxidation for Ag species in the chalcogenide film. Metal-doped ChGs are solid electrolytes that have both ionic and electronic conductivity. The ChG based Programmable Metallization Cell (PMC) is a technology platform that offers electric field dependent resistance switching mechanisms by formation and dissolution of nano sized conductive filaments in a ChG solid electrolyte between oxidizable and inert electrodes. This study identifies silver anode agglomeration in PMC devices following large radiation dose exposure and considers device failure mechanisms via electrical and material characterization. The results demonstrate that by changing device structural parameters, silver agglomeration in PMC devices can be suppressed and reliable resistance switching may be maintained for extremely high doses ranging from 4 Mrad(GeSe) to more than 10 Mrad (ChG). / Dissertation/Thesis / Ph.D. Electrical Engineering 2013

No description available.

No description available.

While the scaling of conventional memories based on floating gate MOSFETs is getting increasingly difficult, novel type of non-volatile memories, such as resistive switching memories, have lately found increased attention by both industry and academia. Resistive switching memory (ReRAM) is being considered one of the prime candidates for next-generation non-volatile memory due to relatively high switching speed, superior scalability, low power consumption, good retention and simplicity of its structure which does not require the expensive real estate structure of the silicon substrate. Furthermore, integration of ReRAM directly into a CMOS low-k/Cu interconnect module would not only reduce latency in connectivity constrained devices, but also would reduce chip's footprint by stacking memory layers on top of the logic circuits. One good candidate is the well-behaved Cu/TaOx/Pt resistive switching device. However, since platinum (Pt) acting as the inert electrode is not an economic choice for industrial production, a Back End of Line (BEOL)-compatible replacement of Pt is highly desirable. A systematic investigation has been conducted and metals such as Ru, Rh and Ir are found to be the best potential candidates to supplant Pt. The device properties of Ru, Rh and Ir based resistive switching devices have been explored in this work. However, the challenges of implementing ReRAM cell into BEOL of CMOS encompass not only the choice of materials of a CBRAM cell proper, but also the way the cell is embedded within BEOL. In case of the inert electrode, the metal interfacing the solid electrolyte (e.g. TaOx) has to be supplanted by a glue layer, and heat transport layer, leading to an engineering task of a composite electrode beyond the requirements of low miscibility with, and low surface diffusivity of the inert electrode with respect of the active metal atoms released by the active electrode (here Cu). The metal of the active electrode (Cu, Ag, Ni) is required to allow for a copious redox reaction but simultaneously preventing reactions with the dielectric. Finally, for the solid electrolyte, a dielectric with a moderate level of defects is preferred which may be controlled, for example by the deposition processes modulating the stoichiometry of the material. This research study begins with exploration of several devices derived from the benchmark device Cu/TaOx/Pt and manufacturing those in Micron nanofabrication and characterization laboratory at Virginia Tech with the latter device used as a benchmark for performance assessment. Electric characterization of the manufactured Cu/TaOx/Ru devices has shown some notable differences between them due to the different formation, shape and rupture of the conductive filament. The inferior switching properties of the Ru device have been attributed to the substantially degraded inertness properties of the Ru electrode as a stopping barrier for Cu as compared to the Pt electrode. To study this degradation effect further, two nominally identical devices however differently embedded on the Si wafer have been fabricated. The electric behavior of the two devices are found to be markedly different and is attributed to the difference in high local temperatures in the device during the switching that cause species interlayer diffusion and trigger undesired chemical reactions. Thus, the embedment of the device has a foremost impact on the intrinsic device performance. To investigate the impact of inert electrode on the endurance of ReRAM memory cells, baseline device Cu/TaOx/Pt/Ti is compared with six devices manufactured with different inert electrode constructions: Pt/Cr, Rh/Cr, Rh/Ti, Rh/Al2O3, Ir/Ti, and Ir/Cr, while the Cu electrode and the TaOx dielectric are identical. Although the glue layers Ti, Cr or Al2O3 are not an inherent part of the device proper, they have a tangible impact on the device endurance as well. It is experimentally demonstrated that inert electrodes with high thermal conductivities have superior endurance properties over an electrode with low thermal conductivity and the heat conductivity of inert electrode has a substantial impact on ReRAM cell performance. Since reset operation is a thermally driven process, frequent switching of resistive memory cell leads to a local accumulation of Joules heat, especially when the switching rate is faster than the heat removal rate. This investigation of local heating effects led to the exploration of non-local heat transfer within a memory array. In a crossbar arranged ReRAM cell array, heat generated in one device spreads via common electrode metal lines to the neighboring cells causing their performance degradation constituting non-local heat transfer mechanism leading to performance deterioration of neighboring cells. In addition to the electrical characterization of devices affected by the remote heat transfer, novel cell array architectures have been proposed and investigated with the goal to significantly mitigate the cell-to-cell thermal crosstalk. One of the possible mitigation measures would be modified cell erasure algorithm. / Doctor of Philosophy / Emerging memory technologies are being intensively investigated for extending Moore's scaling law in the next decade. The resistive random-access memory (ReRAM) is one of the most propitious contenders to replace the current ubiquitous FLASH memory. ReRAM shows unique nanoionics based filamentary switching mechanism. Compared to the current nonvolatile memory based on floating gate MOSFET transistor, the advantages of ReRAM include superior scalability, low power consumption, high OFF-/ON-state resistance ratio, excellent endurance, and long retention of the logic bit states. Besides the nonvolatile memory applications, resistive switching devices implement the function of a memristor which is the fourth basic electrical component and can be used for neuromorphic computing. A ReRAM device is in essence a metal-insulator-metal structure. One of the metal electrodes is called the active electrode and provides the building material for the filamentary connection between the electrodes. An important requirement of the second electrode, called the inert electrode, is to be immiscible with the metal atoms of the active electrode and to exhibit a minimum of susceptibility to structural changes and chemical reactions. This research presents a thorough investigation of the role and properties of the inert electrode and offers guideline for the optimal selection of the inert electrode in a commercially viable product. It has been found out that one important property of the inert electrode is its heat conductivity and also the way the inert electrode is embedded on a substrate. Consequently, the concept of the inert electrode has been replaced by the concept of engineered inert electrode module which evolved from a single metal layer to a multilayer stack displaying glue layers, high thermal conductivity layers dissipating the heat quickly, and diffusion stop layers eliminating unwanted chemical reactions. The investigation of the electro-thermal effects led to the discovery of the cell-to-cell thermal cross talk within the memory array which can seriously affect the performance of cells impacted by the remote heat transfer. When a memory cell is switched repeatedly a considerable amount of heat is dissipated in the cell and the heat may spread to neighboring cells that share the same metal lines. This heat transfer causes degradation of electrical performance of the neighboring cells. A method has been developed to characterize quantitatively how the electrical performance is affected by the thermal cross-talk impacting the electric performance of neighboring cells. Several novel mitigation strategies of new memory array architectures have been proposed and investigated.

No description available.