Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The safety margin makes it difficult to meet the target performance within a limited power budget. This research explores methodologies to minimize the safety margin, thereby improving the energy efficiency of a system. The safety margin can be reduced by either minimizing the variation or adapting to the variation. This research explores three different methods to compensate for variations efficiently. First, post-silicon tuning methods for minimizing variations in 3D ICs are presented. Design methodologies to apply adaptive voltage scaling and adaptive body biasing to 3D ICs and the associated circuit techniques are explored. Second, non-design-intrusive circuit techniques are proposed for adaptation to dynamic variations. This work includes adaptive clock modulation and bias-voltage generation techniques. Third, design-intrusive methods to eliminate the safety margin are proposed. The proposed methodologies can prevent timing-errors in advance with a minimized performance penalty. As a result, the methods presented in this thesis minimize static variations and adapt to dynamic variations, thereby, enabling robust low-power operation of digital systems.

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Gothenburg, Sweden's second-largest city, faces significant environmental challenges due to climate change and risks from rising sea levels. These challenges include eutrophication, spread of environmental toxins, invasive species, and habitat loss. Gothenburg needs more transformative responses, shifting towards adopting water environment changes rather than against it, a concept gaining global traction. This project goaling to making a climate-responsive urban planning to save Gothenburg from lost in economy, ecology, and residents' well-being due to sea level rise. The city is transitioning from a self-centered development approach to one that emphasizes functional ecosystems. This shift includes implementing a multi-scale network of blue-green infrastructures by four methods which are: 1) Improve urban water system; 2) Constructed wetland; 3) Build green road network; 4) Create shore parks for residents. These infrastructures not only maintain the city's water supply system but also create water buffer wetlands, dynamic dykes, and flood bypasses enhancing water environment control. They use low-impact ecological methods for urban runoff regulation and provide ecological and recreational spaces along city-center riverbanks, achieving efficient land use in density city center.

<p>  </p> <p>In the wake of the first Artemis launch, humanity is more focused on space exploration and travel than it has been in the half a century since the Space Race. This time, it’s not enough just to touch down on the Moon; we want to build sustainable homes on the Moon and on Mars. The goal of long-term extra-terrestrial habitation begs the question: how do we design habitats that can protect human life so far from Earth?</p> <p><br></p> <p>The Resilient Extra-Terrestrial Habitat Institute (RETHi) has been operating for four years now building a foundation of ideologies and tools to help answer that question. The institute has developed a control-theoretic approach to habitat resilience based on a state-trigger analysis, a database of potential hazards to a habitat, metrics for resilience quantification, and simulation platforms for design verification.</p> <p><br></p> <p>The combination of these developments allows for the proposition of a resilience-oriented habitat design process. The process takes the shape of a typical systems vee and is tailored to the needs of an extra-terrestrial habitat and the tools available through RETHi. The process proposes a way to build resilience into the requirements development and design verification of extra-terrestrial habitats at three system levels. The result of this study is a discussion on how we design, evaluate, and select safety mechanisms for extra-terrestrial habitats.</p> <p><br></p> <p>Safety mechanisms are selected by simulating the habitat’s response to a disruption when equipped with one safety mechanism at a time and quantifying the habitat’s resilience. Then, the resilience of the habitats with different mechanisms are compared, illuminating the best option. Simulations for each mechanism are performed under a variety of circumstances, changing the time of day and intensity of the disruption as well as the type of repair agent carrying out the mechanism to capture the habitat’s behavior as totally as possible.</p> <p><br></p> <p>This analysis shows how different safety mechanisms performances compare and provides a basis for making design decisions.</p>

This research investigates tolerance strategies for modular systems on a project specific basis. The objective of the proposed research is to form a guideline for optimizing the construction costs/risks with the aim of developing an optimal design of resilient modular systems. The procedures for achieving the research objective included: (a) development of 3D structural analysis models of the modules, (b) strength/stability investigation of the structure, (c) developing the fabrication cost function, (e) checking elastic and inelastic distortion, and (f) constructing the site-fit risk functions. The total site-fit risk function minimizes the cost/risk associated with fabrication, transportation; alignment, rework, and safety, while maximizing stiffness in terms of story drift values for site re-alignment and fitting alternatives. The fabrication cost function was developed by collecting 61 data points for the investigated module chassis using the SAP2000 software while reducing the initial section sizes, in addition to the fabrication costs at each step (61 steps). With the reduction of the structural reinforcement, story drift values increase, therefore there will be a larger distortion in the module. This generic module design procedure models a trade-off between the amount of reinforcement and expected need for significant field alterations. Structural design software packages such as SAP2000, AutoCAD, and Autodesk were used in order to model and test the module chassis. This research hypothesizes that the influential factors in the site-fit risk functions are respectively: fabrication, transportation, alignment, safety, and rework costs/risks. In addition, the site-fit risk function provides a theoretical range of possible solutions for the construction industry. The maximum allowable modular out-of-tolerance value, which requires the minimum amount of cost with respect to the defined function, can be configured using this methodology. This research concludes that over-reinforced or lightly-reinforced designs are not the best solution for mitigating risks, and reducing costs. For this reason the site-fit risk function will provide a range of pareto-optimal building solutions with respect to the fabrication, transportation, safety, alignment, and rework costs/risks.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-06-15T14:23:09Z No. of bitstreams: 1 LEONARDO REZENDE JURACY_DIS.pdf: 2268947 bytes, checksum: bedc63f7c14296e039a798403cdeec80 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-06-26T12:27:11Z (GMT) No. of bitstreams: 1 LEONARDO REZENDE JURACY_DIS.pdf: 2268947 bytes, checksum: bedc63f7c14296e039a798403cdeec80 (MD5) / Made available in DSpace on 2018-06-26T12:45:06Z (GMT). No. of bitstreams: 1 LEONARDO REZENDE JURACY_DIS.pdf: 2268947 bytes, checksum: bedc63f7c14296e039a798403cdeec80 (MD5) Previous issue date: 2018-03-21 / Atualmente, a abordagem s?ncrona ? a mais utilizada em projeto de circuitos integrados por ser altamente automatizado pelas ferramentas comerciais e por incorporar margens de tempo para garantir o funcionamento correto nos piores cen?rios de varia??es de processo e ambiente, limitando otimiza??es no per?odo do rel?gio e aumentando o consumo de pot?ncia. Por um lado, circuitos ass?ncronos apresentam algumas vantagens em potencial quando comparados com os circuitos s?ncronos, como menor consumo de pot?ncia e maior vaz?o de dados, mas tamb?m podem sofrer com varia??es de processo e ambiente. Por outro lado, circuitos resilientes s?o uma alternativa para manter o circuito funcionando na presen?a de efeitos de varia??o. Sendo assim, foi proposto o circuito Blade que combina as vantagens de circuitos ass?ncronos com circuitos resilientes. Blade utiliza latches em sua implementa??o e mant?m seu desempenho em cen?rios de caso m?dio. Independentemente do estilo de projeto (s?ncrono ou ass?ncrono), durante o processo de fabrica??o de circuitos integrados, algumas imperfei??es podem acontecer, causando defeitos que reduzem o rendimento de fabrica??o. Circuitos defeituosos podem apresentar um comportamento falho, gerando uma sa?da diferente da esperada, devendo ser identificados antes de sua comercializa??o. Metodologias de teste podem ajudar na identifica??o e diagn?stico desse comportamento falho. Projeto visando testabilidade (do ingl?s, Design for Testability - DfT) aumenta a testabilidade do circuito adicionando um grau de controlabilidade e observabilidade atrav?s de diferentes t?cnicas. Scan ? uma t?cnica de DfT que fornece para um equipamento de teste externo acesso aos elementos de mem?ria internos do circuito, permitindo inser??o de padr?es de teste e compara??o da resposta. O objetivo deste trabalho ? propor uma abordagem de DfT estrutural, completamente autom?tica e integrada com as ferramentas comerciais de projeto de circuitos, incluindo uma s?rie de m?todos para lidar com os desafios relacionados ao teste de circuitos ass?ncronos e resilientes, com foco no Blade. O fluxo de DfT proposto ? avaliado usando um m?dulo criptogr?fico e um microprocessador. Os resultados obtidos para o m?dulo criptogr?fico mostram uma cobertura de falha de 98,17% para falhas do tipo stuck-at e 89,37% para falhas do tipo path-delay, com um acr?scimo de ?rea de 112,16%. Os resultados obtidos para o microprocessador mostram uma cobertura de 96,04% para falhas do tipo stuck-at e 99,00% para falhas do tipo path-delay, com um acr?scimo de ?rea de 50,57%. / Nowadays, the synchronous circuits design approach is the most used design method since it is highly automated by commercial computer-aided design (CAD) tools. Synchronous designs incorporate timing margins to ensure the correct behavior under the worstcase scenario of process and environmental variations, limiting its clock period optimization and increasing power consumption. On one hand, asynchronous designs present some potential advantages when compared to synchronous ones, such as less power consumption and more data throughput, but they may also suffer with the process and environmental variations. On the other hand, resilient circuits techniques are an alternative to keep the design working in presence of effects of variability. Thus, Blade template has been proposed, combining the advantages of both asynchronous and resilient circuits. The Blade template employs latches in its implementation and supports average-case circuit performance. Independently of the design style (synchronous or asynchronous), during the fabrication process of integrated circuits, some imperfections can occur, causing defects that reduce the fabrication yield. These defective ICs can present a faulty behavior, which produces an output different from the expected, and it must be identified before the circuit commercialization. Test methodologies help to find and diagnose this faulty behavior. Design for Testability (DfT) increases circuit testability by adding a degree of controllability and observability through different test techniques. Scan design is a DfT technique that provides for an external test equipment the access to the internal memory elements of a circuit, allowing test pattern insertion and response comparison. The goal of this work is to propose a fully integrated and automated structural DfT approach using commercial EDA tools and to propose a series of design methods to address the challenges related to testing asynchronous and resilient designs, with focus on Blade template. The proposed DfT flow is evaluated with a criptocore module and a microprocessor. The obtained results for the criptocore module show a fault coverage of 98.17% for stuck-at fault model and 89.37% for path-delay fault model, with an area overhead of 112.16%. The obtained results for the microprocessor show a fault coverage of 96.04% for stuck-at fault model and 99.00% for path-delay fault model, with an area overhead of 50.57%.

The impact of natural disasters is often exacerbated by a disparity between resources for relief and recovery. When the barrio of Punta Santiago in Puerto Rico was devastated by Hurricane Maria in September of 2017, many of its residents lived in the remains of their homes for over a year while they rebuilt from wind damage and flood waters that rose over 6 feet. As climate change leads to an even more constrained timeline for response with increasingly frequent and intense storms, the future of Punta Santiago and other coastal communities worldwide will necessitate strategies ranging from nature-based shore protection systems, coastal setbacks, and managed retreat. This thesis investigates the time disparate processes of disaster relief, recovery, and climate adaptation through the lens of their impact upon the interdependent identities of people and place as informed by theorists and designers including J.B. Jackson and Patrick Geddes. My approach works from the scale of the Antón Ruíz watershed to the delta to uncover the historical and contemporary processes that knit people in the region to the land. I identify commonalities in the immediate recovery needs and long-term resiliency of the community and ecosystems, and seek to support ongoing globally significant research of the rare coastal systems surrounding Punta Santiago. The proposed design, a causeway linking the coast to the hills, dovetails disaster relief and recovery with climate adaptation by providing a persistent connection that restores and reveals the dynamic coastal landscape. / Master of Landscape Architecture / Global warming is correlated with an increase in sea level rise, atmospheric moisture (water content in the air), and surface sea temperatures. The body of research around the complex interaction of these factors is growing, but current projections are that warmer seas will cause more intense hurricanes. Coastal communities, particularly those with fewer economic resources, bear the brunt of this trend and recovery is more difficult with each passing storm. After Hurricane Maria struck in September 2017, many residents of the barrio of Punta Santiago in Puerto Rico lived in the remains of their homes for over a year with little resources to rebuild from the severe wind damage and flood waters that rose over 6 feet. Recovery is still underway almost two years later. A sustainable way forward for Punta Santiago and other coastal communities worldwide necessitates strategies ranging from natural shore stabilization techniques like mangrove buffers and living reefs to restrictions on coastal development, and even the relocation of communities. This thesis investigates the time disparate processes of disaster relief, recovery, and climate adaptation through the lens of their impact upon the interdependent identities of people and place as informed by theorists and designers including J.B. Jackson and Patrick Geddes. My approach works from the scale of the Antón Ruíz watershed to the delta to uncover the historical and contemporary land use that knit people in the region to the land. I identify commonalities in the immediate recovery needs and long-term resiliency of the community and ecosystems, and seek to support ongoing globally significant research of the rare coastal systems surrounding Punta Santiago. The proposed design, a causeway linking the coast to the hills, dovetails disaster relief and recovery with climate adaptation by providing a persistent connection that restores and reveals the dynamic coastal landscape.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-05-21T13:19:36Z No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-06-01T12:13:22Z (GMT) No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) / Made available in DSpace on 2018-06-01T12:33:57Z (GMT). No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) Previous issue date: 2018-03-28 / ? medida que o projeto de VLSI avan?a para tecnologias ultra submicron, as margens de atraso adicionadas para compensar variabilidades de processo de fabrica??o, temperatura de opera??o e tens?o de alimenta??o, tornam-se uma parte significativa do per?odo de rel?gio em circuitos s?ncronos tradicionais. As arquiteturas resilientes a varia??es de atraso surgiram como uma solu??o promissora para aliviar essas margens de tempo projetadas para o pior caso, melhorando o desempenho do sistema e reduzindo o consumo de energia. Essas arquiteturas incorporam circuitos adicionais para detec??o e recupera??o de viola??es de atraso que podem surgir ao projetar o circuito com margens de tempo menores. Os sistemas ass?ncronos apresentam potencial para melhorar a efici?ncia energ?tica e o desempenho devido ? aus?ncia de um sinal de rel?gio global. Al?m disso, os circuitos ass?ncronos s?o conhecidos por serem robustos a varia??es de processo, tens?o e temperatura. Blade ? um modelo que incorpora as vantagens de projeto ass?ncrono e resilientes a varia??es de atraso. No entanto, o Blade ainda apresenta desafios em rela??o ? sua testabilidade, o que dificulta sua aplica??o comercial ou em larga escala. Embora o projeto visando testabilidade com Scan seja amplamente utilizado na ind?stria, os altos custos de sil?cio associados com o seu uso no Blade podem ser proibitivos. Por outro lado, os circuitos ass?ncronos podem apresentar vantagens para testes funcionais, enquanto o circuito resiliente fornece feedback cont?nuo durante o funcionamento normal do circuito, uma caracter?stica que pode ser aplicada para testes concorrentes. Nesta Tese, a testabilidade do Blade ? avaliada sob uma perspectiva diferente, onde o circuito implementado com o Blade apresenta propriedades de confiabilidade que podem ser exploradas para testes. Inicialmente, um m?todo de classifica??o de falhas que relaciona padr?es comportamentais com falhas estruturais dentro da l?gica de detec??o de erro e uma nova implementa??o orientada para teste desse m?dulo de detec??o s?o propostos. A parte de controle ? analisada para falhas internas, e um novo projeto ? proposto, onde o teste ? melhorado e o circuito pode ser otimizado pelo fluxo de projeto. Um m?todo original de medi??o de tempo das linhas de atraso tamb?m ? abordado. Finalmente, o teste de falhas de atrasos em caminhos cr?ticos do caminho de dados ? explorado como uma consequ?ncia natural de um circuito implementado com Blade, onde o monitoramento cont?nuo para detec??o de viola??es de atraso fornece a informa??o necess?ria para a detec??o concorrente de viola??es que extrapolam a capacidade de recupera??o do circuito resiliente. A integra??o de todas as contribui??es fornece uma cobertura de falha satisfat?ria para um custo de ?rea que, para os circuitos avaliados nesta Tese, pode variar de 4,24% a 6,87%, enquanto que a abordagem Scan para os mesmos circuitos apresenta custo que varia de 50,19% a 112,70% em ?rea, respectivamente. As contribui??es desta Tese demonstraram que, com algumas melhorias na arquitetura do Blade, ? poss?vel expandir sua confiabilidade para al?m de um sistema de toler?ncia a viola??es de atraso no caminho de dados, e tamb?m um avan?o para teste de falhas (inclusive falhas online) de todo o circuito, bem como melhorar seu rendimento, e lidar com quest?es de envelhecimento. / As the VLSI design moves into ultra-deep-submicron technologies, timing margins added due to variabilities in the manufacturing process, operation temperature and supply voltage become a significant part of the clock period in traditional synchronous circuits. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins, improving system performance and/or reducing energy consumption. These architectures embed additional circuits for detecting and recovering from timing violations that may arise after designing the circuit with reduced time margins. Asynchronous systems, on the other hand, have a potential to improve energy efficiency and performance due to the absence of a global clock. Moreover, asynchronous circuits are known to be robust to process, voltage and temperature variations. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. Although the design for testability with scan chains is widely applied in the industry, the high silicon costs associated with its use in Blade can be prohibitive. Asynchronous circuits can also present advantages for functional testing, and the timing resilient characteristic provides continuous feedback during normal circuit operation, which can be applied for concurrent testing. In this Thesis, Blade?s testability is evaluated from a different perspective, where circuits implemented with Blade present reliability properties that can be explored for stuck-at and delay faults testing. Initially, a fault classification method that relates behavioral patterns with structural faults inside the error detection logic and a new test-driven implementation of this detection module are proposed. The control part is analyzed for internal faults, and a new design is proposed, where the test coverage is improved and the circuit can be further optimized by the design flow. An original method for time measuring delay lines is also addressed. Finally, delay fault testing of critical paths in the data path is explored as a natural consequence of a Blade circuit, where the continuous monitoring for detecting timing violations provide the necessary feedback for online detection of these delay faults. The integration of all the contributions provides a satisfactory fault coverage for an area overhead that, for the evaluated circuits in this thesis, can vary from 4.24% to 6.87%, while the scan approach for the same circuits implies an area overhead varying from 50.19% to 112.70%, respectively. The contributions of this Thesis demonstrated that with a few improvements in the Blade architecture it is possible to expand its reliability beyond a timing resilient system to delay violations in the data path, but also advances for fault testing (including online faults) of the entire circuit, yield, and aging.